The Phase-I Upgrade of the ATLAS First Level Calorimeter Trigger

Abstract

The ATLAS Level-1 calorimeter trigger is planning a series of upgrades in order to face the challenges posed by the upcoming increase of the LHC luminosity. The trigger upgrade will benefit from new front-end electronics for parts of the calorimeter that provide the trigger system with digital data with a tenfold increase in granularity. This makes possible the implementation of more efficient algorithms than currently used to maintain the low trigger thresholds at much harsher LHC collision conditions. The Level-1 calorimeter system upgrade consists of an active and a passive system for digital data distribution, and three different Feature Extractor systems which run complex algorithms to identify various physics object candidates. The algorithms are implemented in firmware on custom electronics boards with up to four high speed processing FPGAs. The main characteristics of the electronic boards are a high input bandwidth, up to several TB/s per module, implemented through optical receivers, and a large number of on-board tracks providing up to 12.8 Gb/s high speed connections between the receivers and the FPGAs as well as between the FPGAs for data sharing. Prototypes have been built and extensively tested, to prepare for the final design steps and the production of the modules. The contribution will give an overview of the system and present the module designs and results from tests with the prototypes.