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Design and Performance Evaluation of Hybrid Wired-Wireless Network on Chip Interconnect Architectures

  • Priyanka MitraEmail author
  • Bhavna Sharma
  • Vinay Kumar Chandna
  • Vijay Singh Rathore
Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 797)

Abstract

The increasing number of cores in multicores systems-on-chip requires efficient communication infrastructure to satisfy energy and bandwidth requirements of gigascale processors. Hybrid wireless network on chip suffers from the issue of congestion due to availability of single wireless communication within subnet. Thus, the proposed architecture Global Link Architecture (GLA) provides solution by using wireless links and global links. Such architectures improve network throughput and reduce latency by using intelligent routers that balance traffic load. Low cost and efficient deadlock-free deterministic routing schemes GAWIXY for GLA has been proposed to handle congestion of a network and to improve network performance of hybrid wireless network on chip. The proposed architecture has been compared with hybrid wireless network on chip architecture to show its improved performance.

Keywords

Architecture Congestion Deadlock Deterministic Gigascale 

References

  1. 1.
    Benini L, Micheli GD (2002) Networks on chips: a new SoC paradigm. IEEE Comput 35(1):70–78.  https://doi.org/10.1109/2.976921CrossRefGoogle Scholar
  2. 2.
    Pavlidis VF, Friedman EG (2007) 3-D topologies for network-on-chip. IEEE Trans Very Large Scale Integr (VLSI) Syst 15(10):1081–1090.  https://doi.org/10.1109/TVLSI.2007.893649CrossRefGoogle Scholar
  3. 3.
    Shacham A et al (2007) On the design of a photonic network-on-chip. In: Proceedings of first international symposium on networks-on-chips (NOCS), 7–9 May 2007, pp 53,64.  https://doi.org/10.1109/NOCS.2007.35
  4. 4.
    Chang MF et al (2008) CMP network-on-chip overlaid with multi-band RF-interconnect. In: Proceedings of IEEE 14th international symposium high-performance computer architecture (HPCA), pp 191–202.  https://doi.org/10.1109/HPCA.2008.4658639
  5. 5.
    Zhao D, Wang Y (2008) SD-MAC: design and synthesis of a hardware-efficient collision-free QoS-aware MAC protocol for wireless network-on-chip. IEEE Trans Comput 57(9):1230–1245.  https://doi.org/10.1109/TC.2008.86MathSciNetCrossRefzbMATHGoogle Scholar
  6. 6.
    Lee SB et al (2009) A scalable micro wireless interconnect structure for cmps. Mobicom 09:217–228. http://doi.acm.org/10.1145/1614320.1614345
  7. 7.
    Ganguly A et al (2011) Scalable hybrid wireless network-on-chip architectures for multicore systems. IEEE Trans Comput 60(10):1485–1502.  https://doi.org/10.1109/TC.2010.176MathSciNetCrossRefzbMATHGoogle Scholar
  8. 8.
    Deb S et al (2012) Design of an efficient NoC architecture using millimeter-wave wireless links. In: Proceedings of IEEE 13th international symposium on quality electronic design (ISQED), 19–21 Mar 2012, pp165–172.  https://doi.org/10.1109/ISQED.2012.6187490
  9. 9.
    Jain L et al (2007) NIRGAM: a simulator for NoC interconnect routing and application modeling. In: Design, automation and test in Europe conference (DATE), workshop on diagnostic services in network-on-chips, pp 1–2Google Scholar

Copyright information

© Springer Nature Singapore Pte Ltd. 2019

Authors and Affiliations

  • Priyanka Mitra
    • 1
    Email author
  • Bhavna Sharma
    • 1
  • Vinay Kumar Chandna
    • 1
  • Vijay Singh Rathore
    • 1
  1. 1.Department of Computer Science and EngineeringJaipur Engineering College and Research CentreJaipurIndia

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