Design and Performance Evaluation of Hybrid Wired-Wireless Network on Chip Interconnect Architectures

  • Priyanka MitraEmail author
  • Bhavna Sharma
  • Vinay Kumar Chandna
  • Vijay Singh Rathore
Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 797)


The increasing number of cores in multicores systems-on-chip requires efficient communication infrastructure to satisfy energy and bandwidth requirements of gigascale processors. Hybrid wireless network on chip suffers from the issue of congestion due to availability of single wireless communication within subnet. Thus, the proposed architecture Global Link Architecture (GLA) provides solution by using wireless links and global links. Such architectures improve network throughput and reduce latency by using intelligent routers that balance traffic load. Low cost and efficient deadlock-free deterministic routing schemes GAWIXY for GLA has been proposed to handle congestion of a network and to improve network performance of hybrid wireless network on chip. The proposed architecture has been compared with hybrid wireless network on chip architecture to show its improved performance.


Architecture Congestion Deadlock Deterministic Gigascale 


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Copyright information

© Springer Nature Singapore Pte Ltd. 2019

Authors and Affiliations

  • Priyanka Mitra
    • 1
    Email author
  • Bhavna Sharma
    • 1
  • Vinay Kumar Chandna
    • 1
  • Vijay Singh Rathore
    • 1
  1. 1.Department of Computer Science and EngineeringJaipur Engineering College and Research CentreJaipurIndia

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