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Hardware Algorithms

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Principles and Structures of FPGAs

Abstract

Just implementing with hardware is almost nothing to contribute to achieve high performance. The performance of FPGA computing is depends on how to use efficient hardware algorithms for the target application. This chapter introduces various types of hardware algorithms useful for FPGA implementation. First, pipelining is the most popularly used technique. Recently, it is often automatically formed with HLS design tool. Then, general parallel processing techniques are introduced along Flynn’s classic taxonomy. Systolic algorithms and data-flow models are also classic methods researched in 1970s’ and 1980s’, but they have been practically used after large-scale FPGAs are available for computation. Then, stream processing, simple but powerful framework, is introduced with a practical example. Next, cellular automaton, hardware sorting and pattern matching which are important in network processing a killer application of FPGAs are introduced.

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Author information

Authors and Affiliations

  1. RIKEN, Kobe, Japan

    Kentaro Sano

  2. Tokyo Institute of Technology, Tokyo, Japan

    Hiroki Nakahara

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  1. Kentaro Sano
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  2. Hiroki Nakahara
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Correspondence to Kentaro Sano .

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Editors and Affiliations

  1. Keio University, Yokohama, Japan

    Hideharu Amano

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Sano, K., Nakahara, H. (2018). Hardware Algorithms. In: Amano, H. (eds) Principles and Structures of FPGAs. Springer, Singapore. https://doi.org/10.1007/978-981-13-0824-6_6

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  • DOI: https://doi.org/10.1007/978-981-13-0824-6_6

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  • Publisher Name: Springer, Singapore

  • Print ISBN: 978-981-13-0823-9

  • Online ISBN: 978-981-13-0824-6

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