Abstract
Modern digital design techniques are based on globally asynchronous locally synchronous (GALS) architecture which promises to combine the advantages of both synchronous and asynchronous design techniques. System on chip (SOC) based on GALS architecture is divided into many synchronous blocks where each synchronous blocks operate at its own clock. To establish, the communication between the blocks operating in different clock domains is challenging task due to synchronization failure. Therefore, it is desirable to design mixed-clock FIFO (First In First Out) as an interface between different clock domains. In this paper, we have designed an 8 × 32 mixed-clock FIFO which is able to interface two synchronous systems with independent clock frequencies. Our design is simulated using Xilinx 14.7 and modelsim14.4a. Dynamic power of mixed-clock FIFO is 5 mw when write clock and read clock frequencies are 100 MHz which is a most desirable power for an enhanced design. Delay of the design is 4.886 ns.
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Maurya, S., Sharma, S., Saroj, J. (2019). Design of High-Performance Mixed-Clock FIFO. In: Singh, S., Wen, F., Jain, M. (eds) Advances in System Optimization and Control. Lecture Notes in Electrical Engineering, vol 509. Springer, Singapore. https://doi.org/10.1007/978-981-13-0665-5_3
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DOI: https://doi.org/10.1007/978-981-13-0665-5_3
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