Abstract
This paper presents architecture for discrete sine transform (DST) algorithm using VHDL description and its implementation on field programmable gate array (FPGA). Several algorithms have been proposed to implement the DST in its recursive structure form and focus on minimizing the number of additions and multiplications. The hardware designs of the algorithms are largely ignored. The implementation of DST algorithm on the FPGA is motivated by the fact that large memory FPGAs are now available providing a platform for processing real-time algorithms on application-specific hardware with substantially higher performance.
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Jain, A., Pandey, N., Jain, P. (2019). FPGA-Based Architecture for Implementation of Discrete Sine Transform. In: Singh, S., Wen, F., Jain, M. (eds) Advances in System Optimization and Control. Lecture Notes in Electrical Engineering, vol 509. Springer, Singapore. https://doi.org/10.1007/978-981-13-0665-5_2
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DOI: https://doi.org/10.1007/978-981-13-0665-5_2
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