Skip to main content
SpringerLink
Log in

SSD Reliability Assessment and Improvement

  • Chapter
  • First Online:
Inside Solid State Drives (SSDs)

Part of the book series: Springer Series in Advanced Microelectronics ((MICROELECTR.,volume 37))

Abstract

Solid State Drives (SSDs) are one of the electronic systems with the highest development rate in the last decade [1]. Their adoption as a hard disk drive (HDD) replacement in hyper scale environments like cloud computing and big data servers, as well as in consumer electronics, is relentless.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 169.00
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 219.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 219.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

References

  1. http://www.storagesearch.com/chartingtheriseofssds.html. Accessed 2018

  2. R. Micheloni, S. Aritome, L. Crippa, Array architectures for 3-D NAND flash memories. Proc. IEEE 105(9), 1634–1649 (2017)

    Article  Google Scholar 

  3. L. Zuolo, C. Zambelli, R. Micheloni, P. Olivo, Solid-state drives: memory driven design methodologies for optimal performance. Proc. IEEE 105(9), 1589–1608 (2017)

    Article  Google Scholar 

  4. N.R. Mielke, R.E. Frickey, I. Kalastirsky, M. Quan, D. Ustinov, V.J. Vasudevan, Reliability of solid-state drives based on NAND flash memory. Proc. IEEE 105(9), 1725–1750 (2017)

    Article  Google Scholar 

  5. W. Jiang, C. Hu, Y. Zhou, A. Kanevsky, Are disks the dominant contributor for storage failures?: a comprehensive study of storage subsystem failure characteristics. ACM Trans. Storage 4(3), 7 (2008)

    Article  Google Scholar 

  6. L. Bairavasundaram, G. Goodson, S. Pasupathy, J. Schindler, An analysis of latent sector errors in disk drives, in Proceedings of the ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Systems, 2007, pp. 289–300

    Google Scholar 

  7. L. Bairavasundaram, A. Arpaci-Dusseau, G. Goodson, B. Schroeder, An analysis of data corruption in the storage stack. ACM Trans. Storage 4(3), 7 (2008)

    Article  Google Scholar 

  8. B. Schroeder, G. Gibson, Understanding disk failure rates: what does an MTTF of 1,000,000 hours mean to you? ACM Trans. Storage 3(3), 8 (2007)

    Article  Google Scholar 

  9. JEDEC, JESD218B Solid-State Drive (SSD) Requirements and Endurance Test Method (2016)

    Google Scholar 

  10. N. Mielke, Accelerated testing of radiation-induced soft errors in solid-state drives. IEEE Trans. Device Mater. Rel. 15(4), 552–558 (2015)

    Article  Google Scholar 

  11. F. Masuoka, M. Momodomi, Y. Iwata, R. Shirota, New ultra high density EPROM and flash EPROM cell with NAND structure, in IEEE IEDM Technical Digest pp. 552–555 (1987)

    Google Scholar 

  12. M. Lenzlinger, E.H. Snow, Fowler-Nordheim tunneling into thermally grown SiO2. J. Appl. Phys. 40, 273–283 (1969)

    ADS  Google Scholar 

  13. M. Momodomi, T. Tanaka, Y. Iwata, Y. Tanaka, H. Oodaira, Y. Itoh, R. Shirota, K. Ohuchi, F. Masuoka, A 4 Mb NAND EEPROM with Tight Programmed Vt Distribution. IEEE J. Solid State Circ. 26(4), 492–496 (1991)

    Article  ADS  Google Scholar 

  14. G.J. Hemink, T. Tanaka, T. Endoh, S. Aritome, R. Shirota, Fast and accurate programming method for multi-level NAND EEPROMs, in VLSI Symposium on Technology and Circuits, June 1995, pp. 129–130

    Google Scholar 

  15. A. Chimenton, P. Pellati, P. Olivo, Analysis of erratic bits in flash memories. IEEE Trans. Devices Mater. Reliab. 1(4), 179–184 (2001)

    Article  Google Scholar 

  16. M. Momodomi, Y. Itoh, R. Shirota, Y. Iwata, R. Nakayama, R. Kirisawa, T. Tanaka, S. Aritome, T. Endoh, K. Ohuchi, F. Masuoka, An Experimental 4-Mbit CMOS EEPROM with a NAND-structured cell. IEEE J. Solid State Circ. 24(5), 1238–1243 (1989)

    Article  ADS  Google Scholar 

  17. C. Monzio Compagnoni, A. Goda, A.S. Spinelli, P. Feeley, A.L. Lacaita, A. Visconti, Reviewing the evolution of the NAND flash technology. Proc. IEEE 105(9), 1609–1633 (2017)

    Article  Google Scholar 

  18. T. Parnell, N. Papandreou, T. Mittelholzer, H. Pozidis, Modelling of the threshold voltage distributions of sub-20 nm NAND flash memory, in IEEE Global Communications Conference (Austin, TX, 2014), pp. 2351–2356

    Google Scholar 

  19. K. Lee, M. Kang, S. Seo, D. Kang, D.H. Li, Y. Hwang, H. Shin, Separation of corner component in TAT mechanism in retention characteristics of Sub 20-nm NAND flash memory. IEEE Elect. Device Lett. 35(1), 51–53 (2014)

    Article  ADS  Google Scholar 

  20. G.J. Hemink, K. Shimizu, S. Aritome, R. Shirota, Trapped hole enhanced stress induced leakage currents in NAND EEPROM tunnel oxides, in Proceedings of International Reliability Physics Symposium, Apr 1996, pp. 117–121

    Google Scholar 

  21. K. Mizoguchi, T. Takahashi, S. Aritome, K. Takeuchi, Data-retention characteristics comparison of 2D and 3D TLC NAND flash memories, in 2017 IEEE International Memory Workshop (IMW) (Monterey, CA, 2017), pp. 1–4

    Google Scholar 

  22. A. Chimenton, C. Zambelli, P. Olivo, A statistical model of erratic behaviors in flash memory arrays. IEEE Trans. Electr. Devices 58(11), 3707–3711 (2011)

    Article  ADS  Google Scholar 

  23. C. Zambelli, P. Olivo, L. Crippa, A. Marelli, R. Micheloni, Uniform and concentrated read disturb effects in mid-1X TLC NAND flash memories for enterprise solid state drives, in 2017 IEEE International Reliability Physics Symposium (IRPS), (Monterey, CA, 2017), pp. PM-5.1–PM-5.4

    Google Scholar 

  24. H.H. Wang, P.S. Shieh, C.T. Huang, K. Tokami, R. Kuo, S.H. Chen, H.C. Wei, S. Pittikoun, S. Aritome, a new read-disturb failure mechanism caused by boosting hot-carrier injection effect in MLC NAND flash memory, in IEEE International Memory Workshop, May 2009, pp. 1–2

    Google Scholar 

  25. J. Lee, S. Hur, J. Choi, Effects of floating-gate interference on NAND flash memory cell operation. IEEE Elect. Device Lett. 23(5), 264–266 (2002)

    Article  ADS  Google Scholar 

  26. J. Lee, C. Lee, M. Lee, H. Kim, K. Park, W. Lee, A new programming disturbance phenomenon in NAND flash memory by source/drain hot-electrons generated by GIDL current, in Non-volatile Semiconductor Memory Workshop, Feb 2006, pp. 31–33

    Google Scholar 

  27. S. Satoh, H. Hagiwara, T. Tanzawa, K. Takeuchi, R. Shirota, A novel isolation-scaling technology for NAND EEPROMs with the minimized program disturbance, in IEDM Technical Digest, Dec 1997, pp. 291–294

    Google Scholar 

  28. N. Mielke et al., Bit error rate in NAND flash memories, in Proceedings of IEEE International Reliability Physics Symposium Phoenix, Apr 2008, (AZ, USA), pp. 9–19

    Google Scholar 

  29. C. Zambelli, A. Marelli, R. Micheloni, P. Olivo, Modeling the endurance reliability of intradisk RAID solutions for Mid-1X TLC NAND flash solid-state drives, in IEEE Transactions on Device and Materials Reliability, Dec 2017, vol. 17, no. 4, pp. 713–721

    Article  Google Scholar 

  30. G. Dong, N. Xie, T. Zhang, Enabling NAND flash memory use Soft-decision error correction codes at minimal read latency overhead. IEEE Trans. Circ. Syst. I Regul. Paper 60(9), 2412–2421 (2013)

    Article  Google Scholar 

  31. R. Micheloni, A. Marelli, R. Ravasio, Error Correction Codes for Non-Volatile Memories, Springer (2008)

    Google Scholar 

  32. Micron Corporation, TN-29–42: Wear-Leveling Techniques in NAND Flash Devices, Application Note, 2008

    Google Scholar 

  33. H. Belgal, Apparatus, system, and method for improving read endurance for a nonvolatile memory. U.S. Patent 8954650B2, 10 Feb 2015

    Google Scholar 

  34. J. Cha, S. Kang, Data randomization scheme for endurance enhancement and interference mitigation of multilevel flash memory devices. ETRI J. 35(1), 166–169 (2013)

    Article  Google Scholar 

  35. P. Muroke, Flash memory field failure mechanisms, in 2006 IEEE International Reliability Physics Symposium Proceedings (San Jose, CA, 2006), pp. 313–316

    Google Scholar 

  36. C. Zambelli, P. King, P. Olivo, L. Crippa, R. Micheloni, Power-supply impact on the reliability of mid-1X TLC NAND flash memories, in 2016 IEEE International Reliability Physics Symposium (IRPS), (Pasadena, CA, 2016), pp. 2B-3-1–2B-3-6

    Google Scholar 

  37. Y. Li, 3 Bit Per Cell NAND Flash Memory on 19 nm Technology, Flash Memory Summit, Aug 2012

    Google Scholar 

  38. Micron Corporation, Comparison of Client and Enterprise SSD Data Path Protection, Application Note (2011)

    Google Scholar 

  39. SMART Storage Systems, Power Failure Protection, Application Note (2012)

    Google Scholar 

  40. JEDEC, JESD219 Solid-State Drive (SSD) Endurance Workloads (2012)

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Engineering Department, Università di Ferrara, Ferrara, Italy

    C. Zambelli & P. Olivo

Authors
  1. C. Zambelli
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. P. Olivo
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to C. Zambelli .

Editor information

Editors and Affiliations

  1. Microsemi Corporation, Vimercate, Monza e Brianza, Italy

    Rino Micheloni

  2. Microsemi Corporation, Vimercate, Monza e Brianza, Italy

    Alessia Marelli

  3. Lightbits Labs, San Jose, California, USA

    Kam Eshghi

Rights and permissions

Reprints and permissions

Copyright information

© 2018 Springer Nature Singapore Pte Ltd.

About this chapter

Check for updates. Verify currency and authenticity via CrossMark

Cite this chapter

Zambelli, C., Olivo, P. (2018). SSD Reliability Assessment and Improvement. In: Micheloni, R., Marelli, A., Eshghi, K. (eds) Inside Solid State Drives (SSDs). Springer Series in Advanced Microelectronics, vol 37. Springer, Singapore. https://doi.org/10.1007/978-981-13-0599-3_8

Download citation

Publish with us

Policies and ethics

Search

Navigation