Reduction of Kickback Noise in a High-Speed, Low-Power Domino Logic-Based Clocked Regenerative Comparator
The comparator is the most significant element in the design of ADCs. Also there is a lot of demand for low-power, high-speed VLSI circuits. Therefore to maximize power efficiency and speed in ADCs, there is a desire to design high-performance clocked regenerative comparators. The regenerative latch of the comparator is responsible for taking decisions quickly and accurately. Normally, the accuracy of an ADC is degraded due to disturbance in the input voltage called kickback noise, which usually occurs with large variations of voltage at coupled regenerative nodes. This paper describes an analysis of the minimization of kickback noise in a clocked regenerative double tail comparator. To improve further on the double tail comparator, a new domino logic-based regenerative comparator is realized with high speed, low power and reduced kickback noise at low supply voltages. The simulated results using 130 nm CMOS technology confirm the theoretical results. The analysis of the proposed design demonstrates that kickback noise, power, and delay are considerably reduced. The simulation work was carried out using Mentor Graphics tools.
KeywordsClocked regenerative comparators Kickback noise Domino logic CMOS technology
The authors gratefully acknowledge Annamacharya Institute of Technology & Sciences, Rajampet, India and KL University, Vijayawada, India for the support given to carry out this work. The authors would like to extend their gratitude to Prof. B. Abdul Rahim, Mr. S. Fahimuddin, and Dr. G. Vinith Kumar for the stimulating discussions.
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