Advertisement

Compiler-Directed Energy Efficiency

  • Jawad Haj-Yahya
  • Avi Mendelson
  • Yosi Ben Asher
  • Anupam Chattopadhyay
Chapter
Part of the Computer Architecture and Design Methodologies book series (CADM)

Abstract

Modern superscalar CPUs contain large complex structures and diverse execution units, consuming wide dynamic power range. Building power delivery network for the worst-case power consumption is not energy efficient and often impossible to fit in small systems. Instantaneous power excursions can cause voltage droops. Power management algorithms are too slow to respond to instantaneous events. In this work, we propose a novel compiler-directed framework to address this problem. The framework is validated on a 4th Generation Intel® Core™ processor and with simulator on output trace. Up to 16% performance speedup is measured over baseline for the SPEC CPU2006 benchmarks.

References

  1. 1.
    Yahalom, Gilad, Omer Vikinski, and Gregory Sizikov. Architecture constraints over dynamic current consumption. Electrical Performance of Electronic Packaging, 2008 IEEE-EPEP. IEEE, 2008.Google Scholar
  2. 2.
    Wechsler, O. 2006. Inside Intel® Core™ microarchitecture: Setting new standards for energy-efficient performance. Technology, 1.Google Scholar
  3. 3.
    Charles, J., Jassi, P., Ananth, N. S., Sadat, A., & Fedorova, A. 2009, October. Evaluation of the Intel® Core™ i7 Turbo Boost feature. In Workload Characterization, 2009. IISWC 2009. IEEE International Symposium on (pp. 188–197). IEEE.Google Scholar
  4. 4.
    Lattner, Chris, and Vikram Adve. “LLVM: A compilation framework for lifelong program analysis & transformation.” Code Generation and Optimization, 2004. CGO 2004. International Symposium on. IEEE, 2004.Google Scholar
  5. 5.
    Jain, Tarush, and Tanmay Agrawal. “The Haswell Microarchitecture-4th Generation Processo”.Google Scholar
  6. 6.
    Hammarlund, Per, et al. “4th Generation Intel® Core™ Processor, codenamed Haswell.” (2013): 1–1.Google Scholar
  7. 7.
    Jawad Haj-Yihia, Power Profiling of third droop voltage-emergencies tool, 2014, from Haifa University: https://drive.google.com/folderview?id=0B3IgzCqRS5Q_NDZ0dWxZeTdHV2c&usp=sharing.
  8. 8.
    Brooks and M. Martonosi, “Dynamic thermal management for high-performance microprocessors,” in Proc. Int. Symp. On High Performance Computer Architecture, Jan. 2001, pp. 171–182.Google Scholar
  9. 9.
    K. Skadron, “Hybrid architectural dynamic thermal management,” in Proc. Design, Automation & Test in Europe Conf., Mar. 2004.Google Scholar
  10. 10.
    S. Heo, K. Barr, and K. Asanovic, “Reducing power density through activity migration,” in Proc. Int. Symp. Low Power Electronics & Design, Aug. 2003, pp. 217–222.Google Scholar
  11. 11.
    Intel while paper, “Measuring Processor Power, TDP vs. ACP” http://www.intel.com/content/dam/doc/white-paper/resources-xeon-measuring-processor-power-paper.pdf, 2011.
  12. 12.
    M. Popovich, A. V. Mezhiba, and E. G. Friedman, Power Distribution Networks With On-Chip Decoupling Capacitors. New York: Springer, 2008.Google Scholar
  13. 13.
    Patrik Larsson, “Resonance and Damping in CMOS Circuits with On-Chip Decoupling Capacitance,” IEEE Trans. on CAS-I, pp. 849–858, Aug. 1998.Google Scholar
  14. 14.
    Reddi, Vijay Janapa, and Meeta Sharma Gupta. “Resilient Architecture Design for Voltage Variation.” Synthesis Lectures on Computer Architecture 8.2 (2013): 1–138.Google Scholar
  15. 15.
    Kim, Youngtaek, et al. “Audit: Stress testing the automatic way.” Microarchitecture (MICRO), 2012 45th Annual IEEE/ACM International Symposium on. IEEE, 2012.Google Scholar
  16. 16.
    Intel Corporation. 2009. Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 11.1 Design Guidelines. Reference Number 321736, Revision 002, September, 2009.Google Scholar
  17. 17.
    Zhang, Michael T. “Powering Intel (r) Pentium (r) 4 generation processors.” Electrical Performance of Electronic Packaging, 2001. IEEE, 2001.Google Scholar
  18. 18.
    Miller, Timothy N., et al. “VRSync: characterizing and eliminating synchronization-induced voltage emergencies in many-core processors.” ACM SIGARCH Computer Architecture News. Vol. 40. No. 3. IEEE Computer Society, 2012.Google Scholar
  19. 19.
    Kanev, Svilen, et al. “Measuring code optimization impact on voltage noise.” Change 40 (2013): 20.Google Scholar
  20. 20.
    Reddi, Vijay Janapa, et al. “Predicting voltage droops using recurring program and microarchitectural event activity.” IEEE micro 30.1 (2010): 110.Google Scholar
  21. 21.
    Lefurgy, Charles R., et al. “Active management of timing guardband to save energy in POWER7.” proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture. ACM, 2011.Google Scholar
  22. 22.
    Austin, Todd M. “DIVA: A reliable substrate for deep submicron microarchitecture design.” Microarchitecture, 1999. MICRO-32. Proceedings. 32nd Annual International Symposium on. IEEE, 1999.Google Scholar
  23. 23.
    Mukherjee, Shubhendu S., Michael Kontz, and Steven K. Reinhardt. “Detailed design and evaluation of redundant multi-threading alternatives.” Computer Architecture, 2002. Proceedings. 29th Annual International Symposium on. IEEE, 2002.Google Scholar
  24. 24.
    Reddi, Vijay Janapa, et al. “Voltage emergency prediction: Using signatures to reduce operating margins.” High Performance Computer Architecture, 2009. HPCA 2009. IEEE 15th International Symposium on. IEEE, 2009.Google Scholar
  25. 25.
    Joseph, Russ, David Brooks, and Margaret Martonosi. “Control techniques to eliminate voltage emergencies in high performance processors.” High-Performance Computer Architecture, 2003. HPCA-9 2003. Proceedings. The Ninth International Symposium on. IEEE, 2003.Google Scholar
  26. 26.
    Toburen, Mark C. “Power analysis and instruction scheduling for reduced di/dt in the execution core of high-performance microprocessors.” 1999.Google Scholar
  27. 27.
    SPEC 2006; Standard Performance Evaluation Corporation, www.spec.org/.
  28. 28.
    Firasta, Nadeem, et al. “Intel avx: New frontiers in performance improvements and energy efficiency.” Intel white paper, 2008.Google Scholar
  29. 29.
    Shao, Yakun Sophia, and David Brooks. “Energy characterization and instruction-level energy model of Intel’s Xeon Phi processor.” Low Power Electronics and Design (ISLPED), 2013 IEEE International Symposium on. IEEE, 2013.Google Scholar
  30. 30.
    Hähnel, Marcus, et al. “Measuring energy consumption for short code paths using RAPL.” ACM SIGMETRICS Performance Evaluation Review 40.3 (2012): 13–17.Google Scholar
  31. 31.
    A. Yasin, “A Top-Down Method for Performance Analysis and Counters Architecture,” presented at the Performance Analysis of Systems and Software (ISPASS), 2014 IEEE International Symposium on, 2014.Google Scholar
  32. 32.
    Kihwan C., Soma, R., Pedram, M. Fine-grained dynamic voltage and frequency scaling for precise energy and performance tradeoff based on the ratio of off-chip access to on-chip computation times. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, 24(1), 18–28, January 2005.Google Scholar
  33. 33.
    Grochowski, Ed, Dave Ayers, and Vivek Tiwari. “Microarchitectural simulation and control of di/dt-induced power supply voltage variation.” High-Performance Computer Architecture, 2002. Proceedings. Eighth International Symposium on. IEEE, 2002.Google Scholar
  34. 34.
    Gupta, Meeta Sharma, et al. “DeCoR: A delayed commit and rollback mechanism for handling inductive noise in processors.” High Performance Computer Architecture, 2008. HPCA 2008. IEEE 14th International Symposium on. IEEE, 2008.Google Scholar
  35. 35.
    Ernst, Dan, et al. “Razor: A low-power pipeline based on circuit-level timing speculation.” Microarchitecture, 2003. MICRO-36. Proceedings. 36th Annual IEEE/ACM International Symposium on. IEEE, 2003.Google Scholar
  36. 36.
    Ernst, Dan, et al. “Razor: circuit-level correction of timing errors for low-power operation.” IEEE Micro 24.6 (2004): 10–20.Google Scholar
  37. 37.
    Gupta, Meeta Sharma, et al. “Towards a software approach to mitigate voltage emergencies.” Low Power Electronics and Design (ISLPED), 2007 ACM/IEEE International Symposium on. IEEE, 2007.Google Scholar
  38. 38.
    Reddi, Vijay Janapa, et al. “Eliminating voltage emergencies via software-guided code transformations.” ACM Transactions on Architecture and Code Optimization (TACO) 7.2 (2010b): 12.Google Scholar
  39. 39.
    Reddi, Vijay Janapa, et al. “Voltage smoothing: Characterizing and mitigating voltage noise in production processors via software-guided thread scheduling.” Microarchitecture (MICRO), 2010 43rd Annual IEEE/ACM International Symposium on. IEEE, 2010a.Google Scholar
  40. 40.
    Reddi, Vijay Janapa, et al. “Voltage noise in production processors.” IEEE micro 31.1 (2011): 20–28.Google Scholar
  41. 41.
    Intel 64 and IA-32 Architectures Software Developer’s Manual, Volume 3, Section 14.9 as of August 2014.Google Scholar
  42. 42.
    Kim, Youngtaek. Characterization and management of voltage noise in multi-core, multi-threaded processors. Diss. 2013.Google Scholar

Copyright information

© Springer Nature Singapore Pte Ltd. 2018

Authors and Affiliations

  • Jawad Haj-Yahya
    • 1
  • Avi Mendelson
    • 2
  • Yosi Ben Asher
    • 3
  • Anupam Chattopadhyay
    • 4
  1. 1.School of Computer Science and EngineeringNanyang Technological UniversitySingaporeSingapore
  2. 2.Department of Computer Science DepartmentTechnion—Israel Institute of TechnologyHaifaIsrael
  3. 3.Department of Computer ScienceUniversity of HaifaHaifaIsrael
  4. 4.School of Computer Science and EngineeringNanyang Technological UniversitySingaporeSingapore

Personalised recommendations