Power Modeling at High-Performance Computing Processors

  • Jawad Haj-Yahya
  • Avi Mendelson
  • Yosi Ben Asher
  • Anupam Chattopadhyay
Part of the Computer Architecture and Design Methodologies book series (CADM)


A detailed analysis of power consumption at low-system levels becomes important as a means for reducing the overall power consumption of a system and in order to gain performance by avoiding thermal hotspots that reduce system’s frequency. This work presents a new power estimation method that allows understanding the contribution of different architectural components on the power breakdown of an application. To demonstrate the usefulness of the new proposed tool and methodology, we choose to examine this new methodology while using modern processor architecture such as the newly released Intel Skylake processor while executing the entire SPEC CPU2006 benchmark suite. This chapter will provide a detailed power and performance characterization report for the SPEC CPU2006 benchmarks, analysis of the data using side-by-side power, and performance breakdowns, as well as few other interesting case studies.


  1. 1.
    TOP 500 SUPERCOMPUTER SITES, (accessed December 12, 2013).
  2. 2.
    THE GREEN500 SITES, (accessed December 12, 2013).
  3. 3.
    Asanovic, K., Bodik, R., Demmel, J., Keaveny, T., Keutzer, K., Kubiatowicz, J., Morgan, N., Patterson, D., Sen, K., Wawrzynek, J. and Wessel, D., 2009. A view of the parallel computing landscape. Communications of the ACM, 52(10), pp. 56–67.Google Scholar
  4. 4.
    Haj-Yihia, Jawad, et al. “Compiler-directed power management for superscalars.” ACM Transactions on Architecture and Code Optimization (TACO) 11.4 (2015): 48.Google Scholar
  5. 5.
    Merkel, A. and Bellosa, F., 2006, April. Balancing power consumption in multiprocessor systems. In ACM SIGOPS Operating Systems Review (Vol. 40, No. 4, pp. 403–414). ACM.Google Scholar
  6. 6.
    Bhattacharjee, A. and Martonosi, M., 2009, June. Thread criticality predictors for dynamic performance, power, and resource management in chip multiprocessors. In ACM SIGARCH Computer Architecture News (Vol. 37, No. 3, pp. 290–301). ACM.Google Scholar
  7. 7.
    Lee, K.J. and Skadron, K., 2005, April. Using performance counters for runtime temperature sensing in high-performance processors. In Parallel and Distributed Processing Symposium, 2005. Proceedings. 19th IEEE International (pp. 8-pp). IEEE.Google Scholar
  8. 8.
    Bircher, W.L. and John, L.K., 2007, April. Complete system power estimation: A trickle-down approach based on performance events. In Performance Analysis of Systems & Software, 2007. ISPASS 2007. IEEE International Symposium on (pp. 158–168). IEEE.Google Scholar
  9. 9.
    Intel Corporation, “Intel® 64 and IA-32 Architectures Optimization Reference Manual, Appendix B.1” Intel. (as of August 2014).Google Scholar
  10. 10.
    Isci, Canturk, et al. “An analysis of efficient multi-core global power management policies: Maximizing performance for a given power budget.” Proceedings of the 39th annual IEEE/ACM international symposium on microarchitecture. IEEE Computer Society, 2006.Google Scholar
  11. 11.
    Rotem, Efraim, et al. “Power-management architecture of the intel microarchitecture code-named Sandy Bridge.” IEEE Micro 32.2 (2012): 0020-27.Google Scholar
  12. 12.
    Rotem, Efraim, et al. “Energy Aware Race to Halt: A Down to EARtH Approach for Platform Energy Management.” (2012): 1–1.Google Scholar
  13. 13.
    David, H., Gorbatov, E., Hanebutte, U.R., et al.: RAPL: memory power estimation and capping. In: 2010 ACM/IEEE International Symposium on Low-Power Electronics and Design (ISLPED), pp. 189–194. IEEE (2010).Google Scholar
  14. 14.
    Jawad Haj-Yihia, Ahmad Yasin, Yosi ben asher, Avi Mendelson, “Core Power breakdown tool”, 2016.Google Scholar
  15. 15.
    Bhunia, S., Mukhopadhyay, S. (eds.): Low-Power Variation-Tolerant Design in Nanometer Silicon. Springer Verlag (2010).Google Scholar
  16. 16.
    Bellosa, F.: The benefits of event: driven energy accounting in power-sensitive systems. In: Proceedings of the 9th Workshop on ACM SIGOPS European Workshop: Beyond the PC: New Challenges for the Operating System, pp. 37–42. ACM (2000).Google Scholar
  17. 17.
    Powell, Michael D., et al. “CAMP: A technique to estimate per-structure power at run-time using a few simple parameters.” High Performance Computer Architecture, 2009. HPCA 2009. IEEE 15th International Symposium on. IEEE, 2009.Google Scholar
  18. 18.
    Bertran, Ramon, et al. “Decomposable and responsive power models for multicore processors using performance counters.” Proceedings of the 24th ACM International Conference on Supercomputing. ACM, 2010.Google Scholar
  19. 19.
    Bertran, Ramon, et al. “A systematic methodology to generate decomposable and responsive power models for CMPs.” IEEE Transactions on Computers 62.7 (2013): 1289–1302.Google Scholar
  20. 20.
    A. Yasin, “A Top-Down Method for Performance Analysis and Counters Architecture,” presented at the Performance Analysis of Systems and Software (ISPASS), 2014 IEEE International Symposi-um on, 2014.Google Scholar
  21. 21.
    Intel Corporation, “Intel open source”, online: [accesses October 8, 2015].
  22. 22.
    Isci, C., Martonosi, M.: Runtime power monitoring in high-end processors: Methodology and empirical data. In: Proceedings of the 36th Annual IEEE/ACM International Symposium on Microarchitecture, p. 93. IEEE Computer Society (2003).Google Scholar
  23. 23.
    Singh, K., Bhadauria, M., McKee, S.A.: Real time power estimation and thread scheduling via performance counters. ACM SIGARCH Computer Architecture News 37(2), 46–55 (2009).Google Scholar
  24. 24.
    Intel® 64 and IA-32 Architectures Software Developer’s Manual. Volume 3A: System Programming Guide, Part 1, [accesses January, 2016a].Google Scholar
  25. 25.
    Firasta, Nadeem, et al. “Intel avx: New frontiers in performance improvements and energy efficiency.” Intel white paper (2008).Google Scholar
  26. 26.
    A. Carvalho, “The New Linux ’perf’ tools,” presented at the Linux Kongress, 2010.Google Scholar
  27. 27.
    A. Kleen, “toplev manual (pmu-tools)”, online: [accesses October 8, 2015].
  28. 28.
    ThinkPad SMAPI kernel module version 0.40.
  29. 29.
    Bertran, R., Gonzàlez, M., Martorell, X., et al.: Counter-Based Power Modeling Methods: Top-Down vs. Bottom-Up. The Computer Journal 56(2), 198–213 (2013).Google Scholar
  30. 30.
    Y. S. Shao and D. Brooks, “ISA-independent workload characterization and its implications for specialized architectures,” in Proceedings of the International Symposium on Performance Analysis of Systems and Software (ISPASS), 2013, pp. 245–255.Google Scholar
  31. 31.
    Y. S. Shao, B. Reagen, G.-Y. Wei, and D. Brooks, “Aladdin: A preRTL, power-performance accelerator simulator enabling large design space exploration of customized architectures,” in Proceedings of the 41st Annual International Symposium on Computer Architecture (ISCA), 2014, pp. 97–108.Google Scholar
  32. 32.
    S. Van den Steen, S. De Pestel, M. Mechri, S. Eyerman, T. Carlson, L. Eeckhout, E. Hagersten, and D. Black-Schaffer. Micro-architecture independent analytical processor performance and power modeling. In Proceedings of the 2015 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), Mar. 2015.Google Scholar
  33. 33.
    Intel Corporation, “6th Generation Intel® Processor Family – Specification update”, online: [accesses August, 2016].
  34. 34.
    Spiliopoulos, Vasileios, Andreas Sembrant, and Stefanos Kaxiras. “Power-sleuth: A tool for investigating your program’s power behavior.” Modeling, Analysis & Simulation of Computer and Telecommunication Systems (MASCOTS), 2012 IEEE 20th International Symposium on. IEEE, 2012.Google Scholar
  35. 35.

Copyright information

© Springer Nature Singapore Pte Ltd. 2018

Authors and Affiliations

  • Jawad Haj-Yahya
    • 1
  • Avi Mendelson
    • 2
  • Yosi Ben Asher
    • 3
  • Anupam Chattopadhyay
    • 4
  1. 1.School of Computer Science and EngineeringNanyang Technological UniversitySingaporeSingapore
  2. 2.Department of Computer Science DepartmentTechnion—Israel Institute of TechnologyHaifaIsrael
  3. 3.Department of Computer ScienceUniversity of HaifaHaifaIsrael
  4. 4.School of Computer Science and EngineeringNanyang Technological UniversitySingaporeSingapore

Personalised recommendations