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Power Management of Modern Processors

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Part of the book series: Computer Architecture and Design Methodologies ((CADM))

Abstract

Recent technology advances have resulted in power being the major concern for digital design. In this chapter, we give introduction to power management at modern processors and present the parameters that affect the energy and power of digital circuits. The state of the art in power management methodology is examined and we present energy efficiency metrics, such as the energy delay. We examine how modern processors utilize features, such as clock gating, power gating and DVFS in order to reduce the overall energy consumption of the platform while maintaining high performance. Finally, we present state-of-the-art techniques that are used today in modern processors.

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Notes

  1. 1.

    The minimum gate-to-source voltage differential that is needed to create a conducting path between the source and drain terminals.

  2. 2.

    Uncore is a term used by Intel to describe the functions of a microprocessor that are not in the core or Graphics, but which must be closely connected to the core to achieve high performance, for example the memory controller.

References

  1. NASA Goddard Institute for Space Studies (n.d.). GISS Surface Temperature Analysis. Accessed November 30, 2010.

    Google Scholar 

  2. NRE (2010) National renewable energy laboratory. URL www.nrel.gov.

  3. de Vries RP (2010) Green chips: A new era for the semiconductor industry. In: Proc. IEEE 2010 Custom Integrated Circuits Conf.

    Google Scholar 

  4. EER (2010) The office of energy efficiency and renewable energy. URL www.eere.energy.gov.

  5. TOP 500 SUPERCOMPUTER SITES, http://www.top500.org/list/2013/06 (accessed December 12, 2013).

  6. THE GREEN500 SITES, http://www.green500.org (accessed December 12, 2013).

  7. Barroso, L.A., Clidaras, J. and Hölzle, U., 2013. The datacenter as a computer: An introduction to the design of warehouse-scale machines. Synthesis lectures on computer architecture, 8(3), pp. 1–154.

    Google Scholar 

  8. M. Poess and R. O. Nambiar, “Energy cost, the key challenge of today’s data centers: A power consumption analysis of TPC-C results,” Proc. VLDB Endowment, vol. 1, no. 2, pp. 1229–1240, Aug. 2008.

    Google Scholar 

  9. R. Buyya, C. Vecchiola, and S. Selvi, Mastering Cloud Computing: Foundations and Applications Programming. Amsterdam, The Netherlands: Elsevier, 2013.

    Google Scholar 

  10. Y. Gao, H. Guan, Z. Qi, B. Wang, and L. Liu, “Quality of service aware power management for virtualized data centers,” J. Syst. Architect., vol. 59, no. 4/5, pp. 245–259, Apr./May 2013.

    Google Scholar 

  11. S. Rivoire, M. Shah, P. Ranganathan, C. Kozyrakis, and J. Meza, “Models and metrics to enable energy efficiency optimizations,” Computer, vol. 40, no. 12, pp. 39–48, Dec. 2007.

    Google Scholar 

  12. K. Bilal, S. Malik, S. Khan, and A. Zomaya, “Trends and challenges in cloud datacenters,” IEEE Cloud Comput., vol. 1, no. 1, pp. 10–20, May 2014.

    Google Scholar 

  13. B. Whitehead, D. Andrews, A. Shah, and G. Maidment, “Assessing the environmental impact of data centres—Part 1: Background, energy use and metrics,” Building Environ., vol. 82, pp. 151–159, Dec. 2014.

    Google Scholar 

  14. V. Mathew, R. K. Sitaraman, and P. J. Shenoy, “Energy-aware load balancing in content delivery networks,” CoRR, vol. abs/1109.5641, 2011.

    Google Scholar 

  15. P. Corcoran and A. Andrae, “Emerging trends in electricity consumption for consumer ICT,” Nat. Univ. Ireland, Galway, Ireland, Tech. Rep., 2013.

    Google Scholar 

  16. Koomey, J., 2011. Growth in data center electricity use 2005 to 2010. A report by Analytical Press, completed at the request of The New York Times, 9.

    Google Scholar 

  17. Van Heddeghem, W., Lambert, S., Lannoo, B., Colle, D., Pickavet, M. and Demeester, P., 2014. Trends in worldwide ICT electricity consumption from 2007 to 2012. Computer Communications, 50, pp. 64–76.

    Google Scholar 

  18. “Energy efficiency policy options for Australian and New Zealand data centers,” The Equipment Energy Efficiency (E3) Program, 2014.

    Google Scholar 

  19. Info-Tech, “Top 10 energy-saving tips for a greener data center,” Info-Tech Research Group, London, ON, Canada, Apr. 2010.

    Google Scholar 

  20. S. Yeo, M. M. Hossain, J.-C. Huang, and H.-H. S. Lee, “ATAC: Ambient temperature-aware capping for power efficient datacenters,” in Proc. ACM SOCC, 2014, pp. 17:1–17:14.

    Google Scholar 

  21. S. Devadas and S. Malik, A survey of optimization techniques targeting low power VLSI circuits,‖ in Proceedings of the 32nd ACM/IEEE Conference on Design Automation, 1995, pp. 242–247.

    Google Scholar 

  22. V. Tiwari, P. Ashar, and S. Malik, “Technology mapping for low power” in Proceedings of the 30th Conference on Design Automation, 1993, pp. 74–79.

    Google Scholar 

  23. Intel math kernel library (MKL). http://software.intel.com/en-us/articles/intel-mkl/.

  24. J. Cebrian et al., Optimized hardware for suboptimal software: The case for SIMD-aware benchmarks, in ISPASS, 2014.

    Google Scholar 

  25. L. Benini, A. Bogliolo, and G. D. Micheli, “A survey of design techniques for system-level dynamic power management” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 8, no. 3, pp. 299–316, 2000.

    Google Scholar 

  26. S. Albers, “Energy-efficient algorithms” Communications of the ACM, vol. 53, no. 5, pp. 86–96, 2010.

    Google Scholar 

  27. V. Venkatachalam and M. Franz, Power reduction techniques for microprocessor systems,‖ ACM Computing Surveys (CSUR), vol. 37, no. 3, pp. 195–237, 2005.

    Google Scholar 

  28. G. Buttazzo, Scalable applications for energy-aware processors,‖ in Embedded Software, 2002, pp. 153–165.

    Google Scholar 

  29. Efraim, R., Ginosar, R., Weiser, C. and Mendelson, A., 2014. Energy aware race to halt: A down to EARtH approach for platform energy management. IEEE Computer Architecture Letters, 13(1), pp. 25–28.

    Google Scholar 

  30. M. Weiser, B. Welch, A. Demers, and S. Shenker, Scheduling for reduced CPU energy,‖ Mobile Computing, pp. 449–471, 1996.

    Google Scholar 

  31. K. Govil, E. Chan, and H. Wasserman, Comparing algorithm for dynamic speed-setting of a low-power CPU,‖ in Proceedings of the 1st Annual International Conference on Mobile Computing and Networking (MobiCom 2005), Berkeley, California, USA, 1995, p. 25.

    Google Scholar 

  32. A. Wierman, L. L. Andrew, and A. Tang, Power-aware speed scaling in processor sharing systems,‖ in Proceedings of the 28th Conference on Computer Communications (INFOCOM 2009), Rio, Brazil, 2009.

    Google Scholar 

  33. L. L. Andrew, M. Lin, and A. Wierman, Optimality, fairness, and robustness in speed scaling designs,‖ in Proceedings of ACM International Conference on Measurement and Modeling of International Computer Systems (SIGMETRICS 2010), New York, USA, 2010.

    Google Scholar 

  34. A. Weissel and F. Bellosa, Process cruise control: event-driven clock scaling for dynamic power management,‖ in Proceedings of the 2002 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, Grenoble, France, 2002, p. 246.

    Google Scholar 

  35. K. Flautner, S. Reinhardt, and T. Mudge, Automatic performance setting for dynamic voltage scaling,‖ Wireless networks, vol. 8, no. 5, pp. 507–520, 2002.

    Google Scholar 

  36. S. Lee and T. Sakurai, Run-time voltage hopping for low-power real-time systems,‖ in Proceedings of the 37th Annual Design Automation Conference, Los Angeles, CA, USA, 2000, pp. 806–809.

    Google Scholar 

  37. J. R. Lorch and A. J. Smith, Improving dynamic voltage scaling algorithms with PACE,‖ ACM SIGMETRICS Performance Evaluation Review, vol. 29, no. 1, p. 61, 2001.

    Google Scholar 

  38. C.-H. R. Wu, “U.S. patent 7352641: Dynamic memory throttling for power and thermal limitations.” Sun Microsystems, Inc., issued 2008.

    Google Scholar 

  39. I. Hur and C. Lin, “A comprehensive approach to DRAM power management,” in Proceedings of the 14th International Symposium on High Performance Computer Architecture (HPCA’08), August 2008.

    Google Scholar 

  40. K.T. Sundararajan, T.M. Jones, and N. Tophamet, “Smart Cache: a self-adaptive cache architecture for energy efficiency,” Int. Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, 2011.

    Google Scholar 

  41. J.R. Srinivasan, “Improving cache utilization,” Technical Report, Univ. of Cambridge, 2011.

    Google Scholar 

  42. Advanced Configuration and Power Interface (ACPI) specification [online], Available: www.acpi.info.

  43. Rotem, E. and Engineer, S.P., 2015, August. Intel Architecture, Code Name Skylake Deep Dive: A New Architecture to Manage Power Performance and Energy Efficiency. In Intel Developer Forum.

    Google Scholar 

  44. Rotem, E., Weiser, U.C., Mendelson, A., Ginosar, R., Weissmann, E. and Aizik, Y., 2016. H-EARtH: Heterogeneous Multicore Platform Energy Management. Computer, 49(10), pp. 47–55.

    Google Scholar 

  45. “Processor Package and Core C-States”. AnandTech. 2013–06-09. Retrieved 2013-10-20.

    Google Scholar 

  46. Rotem, E., Naveh, A., Ananthakrishnan, A., Weissmann, E. and Rajwan, D., 2012. Power-management architecture of the intel microarchitecture code-named sandy bridge. Ieee micro, 32(2), pp. 20–27.

    Google Scholar 

  47. Mahesri, A. and Vardhan, V., 2004, December. Power consumption breakdown on a modern laptop. In International Workshop on Power-Aware Computer Systems (pp. 165–180). Springer, Berlin, Heidelberg.

    Google Scholar 

  48. David, Howard, Chris Fallin, Eugene Gorbatov, Ulf R. Hanebutte, and Onur Mutlu. “Memory power management via dynamic voltage/frequency scaling.” In Proceedings of the 8th ACM international conference on Autonomic computing, pp. 31–40. ACM, 2011.

    Google Scholar 

  49. Rotem, E., Naveh, A., Rajwan, D., Ananthakrishnan, A. and Weissmann, E., 2011, August. Power management architecture of the 2nd generation Intel® Core microarchitecture, formerly codenamed Sandy Bridge. In Hot Chips 23 Symposium (HCS), 2011 IEEE (pp. 1–33). IEEE.

    Google Scholar 

  50. Jahagirdar, S., George, V., Sodhi, I. and Wells, R., 2012, August. Power management of the third generation Intel Core micro architecture formerly codenamed Ivy Bridge. In Hot Chips 24 Symposium (HCS), 2012 IEEE (pp. 1–49). IEEE.

    Google Scholar 

  51. Fayneh, E., Yuffe, M., Knoll, E., Zelikson, M., Abozaed, M., Talker, Y., Shmuely, Z. and Rahme, S.A., 2016, January. 4.1 14 nm 6th-generation Core processor SoC with low power consumption and improved performance. In Solid-State Circuits Conference (ISSCC), 2016 IEEE International (pp. 72–73). IEEE.

    Google Scholar 

  52. Howse, B. and Smith, R., 2015. Tick Tock On The Rocks: Intel Delays 10 nm, Adds 3rd Gen 14 nm Core Product KabyLake.

    Google Scholar 

  53. Intel. Intel® 64 and IA-32 Architectures Optimization Reference Manual, June 2016.

    Google Scholar 

  54. Nalamalpu, A., Kurd, N., Deval, A., Mozak, C., Douglas, J., Khanna, A., Paillet, F., Schrom, G. and Phelps, B., 2015, June. Broadwell: A family of IA 14 nm processors. In VLSI Circuits (VLSI Circuits), 2015 Symposium on (pp. C314-C315). IEEE.

    Google Scholar 

  55. E. Rotem, “Intel® Architecture, Code Name Skylake Deep Dive: A New Architecture to Manage Power Performance and Energy Efficiency,” presented at the Intel Developer Forum (IDF15), 2015.

    Google Scholar 

  56. Isci, C., Martonosi, M.: Runtime power monitoring in high-end processors: Methodology and empirical data. In: Proceedings of the 36th Annual IEEE/ACM International Symposium on Microarchitecture, p. 93. IEEE Computer Society (2003).

    Google Scholar 

  57. Cai, G. and Lim, C.H., 1999. Architectural level power/performance optimization and dynamic power estimation. Cool Chips Tutorial colocated with MICRO32, 621.

    Google Scholar 

  58. D. Brooks, V. Tiwari, and M. Martonosi. Wattch: A Framework for Architectural-Level Power Analysis and Optimization. In Proceedings of the 27th International Symposium on Computer Architecture, pages 83–94, Vancouver, Canada, June 2000.

    Google Scholar 

  59. W. Wu, L. Jin, J. Wang, P. Liu, and S. X.-D. Tan. A systematic method for functional unit power estimation in microprocessors. In Proceedings of the 43rd Conference on Design Automation, July 2006.

    Google Scholar 

  60. J. Peddersen and S. Parameswaran. CLIPPER: counter-based low impact processor power estimation at run-time. In Asia and South Pacific Design Automation Conference, Jan. 2007.

    Google Scholar 

  61. C. Isci and M. Martonosi. Runtime power monitoring in high-end processors: Methodology and emprical data. In 36th International Symposium on Microarchitecture (MICRO 36), pages 93–104, Dec. 2003.

    Google Scholar 

  62. R. Joseph and M. Martonosi. Run-time power estimation in high-performance microprocessors. In International Symposium on Low Power Electronics and Design, pages 135–140, Aug. 2001.

    Google Scholar 

  63. J. Sharkey, A. Buyuktosunoglu, and P. Bose. Evaluating design tradeoffs in on-chip power management for cmps. In Proceedings of the International Symposium on Low Power Electronics and Design, pages 44–49, Aug. 2007.

    Google Scholar 

  64. Powell, Michael D., et al. “CAMP: A technique to estimate per-structure power at run-time using a few simple parameters.” High Performance Computer Architecture, 2009. HPCA 2009. IEEE 15th International Symposium on. IEEE, 2009.

    Google Scholar 

  65. Bellosa, Frank. “The benefits of event: driven energy accounting in power-sensitive systems”. In: Proceedings of the 9th Workshop on ACM SIGOPS European Workshop: Beyond the PC: New Challenges for the Operating System, pp. 37–42. ACM (2000)

    Google Scholar 

  66. Rotem, Efraim, Alon Naveh, Avinash Ananthakrishnan, Eliezer Weissmann, and Doron Rajwan. “Power-management architecture of the intel microarchitecture code-named sandy bridge.” IEEE Micro 32.2 (2012): 0020–27.

    Google Scholar 

  67. B. C. Lee and D. M. Brooks. Accurate and efficient regression modeling for microarchitectural performance and power prediction. In Proceedings of the Twelfth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS XII), Oct. 2006.

    Google Scholar 

  68. P. J. Joseph, K. Vaswani, and M. J. Thazhuthaveetil. Construction and use of linear regression models for processor performance analysis. In Twelfth International Symposium on High Performance Computer Architecture (HPCA), pages 99–108, Feb. 2006.

    Google Scholar 

  69. E. Ipek, S. McKee, B. de Supinski, M. Schulz, and R. Caruana. Efficiently exploring architectural design spaces via predictive modeling. In Proceedings of the Twelfth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS XII), Oct. 2006.

    Google Scholar 

  70. E. Macii and M. Pedram. High-level power modeling, estimation, and optimization. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 17(11):1061–1079, Nov. 1998.

    Google Scholar 

  71. S. Katkoori and R. Vemuri. Architectural power estimation based on behavior level profiling. Journal on VLSI Design, Special Issue on Low Power, 1996.

    Google Scholar 

  72. V. Srinivasan, D. Brooks, Michael Gschwind, P. Bose, V. Zyuban, P. N. Strenski, and P. G. Emma. Optimizing pipelines for power and performance. In Proceedings of the 35th International Symposium on Microarchitecture (MICRO 35), pages 333–344, Nov. 2002.

    Google Scholar 

  73. V. Zyuban and P. Strenski. Unified methodology for resolving power-performance tradeoffs at the microarchitectural and circuit levels. In Proceedings of the International Symposium on Low Power Electronics and Design, pages 166–171, Aug. 2002.

    Google Scholar 

  74. M. T.-C. Lee, V. Tiwari, S. Malik, and M. Fujita. Power analysis and minimization techniques for embedded dsp software. IEEE Transactions on VLSI Systems, 5(1):123–135, Mar. 1997.

    Google Scholar 

  75. P. Landman. High level power estimation. In Proceedings of the International Symposium on Low Power Electronics and Design, pages 29– 35, Aug. 1996.

    Google Scholar 

  76. D. Brooks, V. Tiwari, and M. Martonosi. Wattch: A framework for architectural- level power analysis and optimizations. In Proceedings of the 27th Annual International Symposium on Computer Architecture, pages 83–94, June 2000.

    Google Scholar 

  77. D. M. Brooks, P. Bose, V. Srinivasan, M. K. Gschwind, P. G. Emma, and M. G. Rosenfield. New methodology for early-stage microarchitecture- level power-performance analysis of microprocessors. IBM Journal of Research and Development, 47(5/6):653–670, Sept. 2003.

    Google Scholar 

  78. T. S. Karkhanis and J. E. Smith. A first-order superscalar processor model. In Proceedings of the 31st International Symposium on Computer Architecture (ISCA 31), pages 338–349, June 2004.

    Google Scholar 

  79. D. B. Noonburg and J. P. Shen. Theoretical modeling of superscalar processor performance. In Proceedings of the 27th International Symposium on Microarchitecture (MICRO 27), pages 52–62, Nov. 1994.

    Google Scholar 

  80. E. Rotem, “Intel® Architecture, Code Name Skylake Deep Dive: A New Architecture to Manage Power Performance and Energy Efficiency,” presented at the Intel Developer Forum (IDF15), 2015.

    Google Scholar 

  81. Gonzalez, Ricardo, and Mark Horowitz. “Energy dissipation in general purpose microprocessors,” IEEE J. Solid-State Circuits, Vol. 31, No. 9, Sept. 1996, pp. 1277–1284.

    Google Scholar 

  82. Intel 64 and IA-32 Architectures Software Developer’s Manual, Volume 3, Section 14.9 (as of November 2014).

    Google Scholar 

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Haj-Yahya, J., Mendelson, A., Ben Asher, Y., Chattopadhyay, A. (2018). Power Management of Modern Processors. In: Energy Efficient High Performance Processors. Computer Architecture and Design Methodologies. Springer, Singapore. https://doi.org/10.1007/978-981-10-8554-3_1

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