Low-Power High-Performance Multitransform Architecture Using Run-Time Reconfigurable Adder for FPGA and ASIC Implementation

Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 732)

Abstract

The multistandard transform (MST) architecture for MPEG-1/2/4, H.264 and VC-1 using common sharing distributed arithmetic (CSDA) is more popular in multimedia communications. The CSDA and multitransform architecture have more number of 12-bit and 16-bit adders. In real-time computation, more redundant input data present in the most significant bit (MSB) part. So, in this paper, a detector logic circuit is developed to distinguish unwanted and informative portion of the input data. Then, the detector logic circuit-based run-time reconfigurable adder is designed. The detector result is used to disable the unnecessary computation block within the 12-bit adder, whenever non-informative data present in the input side of the adder. Therefore, it reduces the signal-level changes in the logic gate circuits and proportionally the power consumption becomes less. This improved architecture design is used in the 2D CSDA-MST core to analyse computation speed and power consumption. The proposed adder is evaluated with 12-bit and 16-bit input length. The calculated result shows that 21.6 and 16.25% of active logic gate reduce for 12-bit and 16-bit adder, respectively. Also, synthesized result of the proposed adder-based 2D CSDA-MST core is compared with spurious power suppression technique (SPST) adder-based 2D CSDA-MST core. The major advantage of the proposed adder is less power consumption with miniature overhead of the area. So, the proposed run-time configurable adder-based 2D CSDA-MST core is suitable for low-power and high-speed multimedia applications.

Keywords

Multistandard transform Common sharing distributed arithmetic Ripple carry adder Spurious power suppression technique Detector Selected butterfly Error-compensated error trees 

Notes

Acknowledgements

We would like to thank the Centre for VLSI Design, Department of Electronics and Communication Engineering, K. S. Rangasamy College of Technology, Tiruchengode, Tamil Nadu, for providing the Synopsys EDA tools and various Xilinx FPGA kits.

References

  1. 1.
    Chen, Y.-H., Chen, J.-N., Chang, T.-Y., Lu, C.-W.: High-throughput multistandard transform core supporting MPEG/H.264/VC-1 using common sharing distributed arithmetic. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 22(3) (2014)Google Scholar
  2. 2.
    El-Hadedy, M., Purohit, S., Margala, M., Knapskog, S.J.: Low Latency Transpose Memory for High Throughput Signal Processing. Norwegian University of Science and Technology, Trondheim, Norway (2010)Google Scholar
  3. 3.
    Shams, A.M., Chidanandan, A., Pan, W., Bayoumi, M.A.: NEDA: a low-power high-performance DCT architecture. IEEE Trans. Signal Process. 54(3) (2006)Google Scholar
  4. 4.
    Yu, S., Swartzlander, E.E.: DCT implementation with distributed arithmetic. IEEE Trans. Comput. 50(9) (2001)Google Scholar
  5. 5.
    Hwangbo, W., Kyung, C.-M.: A Multitransform architecture for H.264/AVC high-profile coders. IEEE Trans. Multimedia 12(3) (2010)Google Scholar
  6. 6.
    Chen, K.-H., Chu, Y.-S.: A spurious-power suppression technique for multimedia/DSP applications. IEEE Trans. Circ. Syst. I Regular Papers 56(1) (2009)Google Scholar
  7. 7.
    Sivanandam, K., Kumar, P.: Run time reconfigurable modified vedic multiplier for high speed multimedia applications. In: 2nd International Conference on Computing for Sustainable Global Development, 11th–13th Mar 2015Google Scholar
  8. 8.
    Chen, Y.-H., Chang, T.-Y., Li, C.-Y.: High throughput DA-based DCT with high accuracy error-compensated adder tree. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 19(4) (2011)Google Scholar
  9. 9.
    Chen, K.-H., Guo, J.-I., Wang, J.-S., Yeh, C.-W., Chen, J.-W.: An energy-aware IP core design for the variable-length DCT/IDCT targeting at MPEG4 shape-adaptive transforms. IEEE Trans. Circ. Syst. Video Technol. 15(5) (2005)Google Scholar
  10. 10.
    Fan, C.-P., Su, G.-A.: Fast algorithm and low-cost hardware-sharing design of multiple integer transforms for VC-1. IEEE Trans. Circ. Syst. II Express Briefs 56(10) (2009)Google Scholar
  11. 11.
    Lin, C.-T., Yu, Y.-C., Van, L.-D.: Cost-effective triple-mode reconfigurable pipeline FFT/IFFT/2-D DCT processor. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 16(8) (2008)Google Scholar
  12. 12.
    Xie, J., Meher, P.K.: Hardware-efficient realization of prime-length DCT based on distributed arithmetic. IEEE Trans. Comput. 62(6) (2013)Google Scholar

Copyright information

© Springer Nature Singapore Pte Ltd. 2018

Authors and Affiliations

  1. 1.Department of Electronics and Communication EngineeringK S Rangasamy College of TechnologyTiruchengode, NamakkalIndia

Personalised recommendations