Design and Simulation of OTA Using 45 nm Technology

  • Amit Sharma
  • Sansar Chand
  • Navneet Gill
Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 732)


OTA is very popular in electronics industry due to its large number of applications. Double gate MOSFETs are strong contenders for nanoscale region due to its better control over SCEs. In this paper, emphasis is to design low power, better phase margin OTA using double gate MOSFETs. The simulations are done at 45 nm technology.


Analog tunable circuits Gain Low supply voltage Phase margin DG MOSFETs OTA 


  1. 1.
    International Technology Roadmap for Semiconductor (lTRS), WO I VersionGoogle Scholar
  2. 2.
    Yu, B., Wang, H., Joshi, A., Xiang, Q., Ibok, E., Lin, M.-R.: 15-nm gate length planar CMOS transistor. In: Tech. Dig. IEDM, p. 937 (2001)Google Scholar
  3. 3.
    Taur, Y.: JEEE SpectruIII, vo1. 36, no. 7, pp. 25–29 (1999)Google Scholar
  4. 4.
    Tosaka, T., Suzuki, K., Horie, H., Sugii, T.: Scaling parameter dependent model for sub-threshold swing S in double-gate SOI MOSFET’s. IEEE Electron Device Lett. 15(11), 466–468 (1994)CrossRefGoogle Scholar
  5. 5.
    Wong, H.-S.P.: Beyond the conventional MOSFET. In: Proceedings of 31st European Solid-State Device Research Conference, p. 69 (2001)Google Scholar
  6. 6.
    Razavi, B.: Design of Analog CMOS Amplifier (2001)Google Scholar
  7. 7.
    Reddy, M.V.R., Sharma, D.K., Patil, M.B., Rao, V.R.: Power-area evaluation of various double-gate RF mixer topologies. IEEE Electron Devices Lett. 26, 664 (2005)CrossRefGoogle Scholar
  8. 8.
    Masahara, M., et al.: Demonstration, analysis, and device design considerations for independent DG MOSFETs. IEEE Trans. Electron Dev. 52(9), 2046–2053 (2005)CrossRefGoogle Scholar
  9. 9.
    Roy, K., Mahmoodi, H., Mukhopadhyay, S., Ananthan, H., Bansal, A., Cakici, T.: Double-Gate SOI Devices for Low-Power and High-Performance Applications. Department of Electrical and Computer Engineering, Purdue University, West Lafayette, IN School of Engineering, San Francisco State University (2005)Google Scholar
  10. 10.
    Kim, K., Fossum, J.G.: Optimal Double-Gate MOSFETs: Symmetrical or Asymmetrical Gates? IEEE (1999)Google Scholar
  11. 11.
    Kushwah, R.S., Akashe, S.: Design and analysis of tunable analog circuit using double gate MOSFET at 45 nm CMOS technology. IEEE (2013)Google Scholar

Copyright information

© Springer Nature Singapore Pte Ltd. 2018

Authors and Affiliations

  1. 1.C.Sc. DepartmentDAV CollegeJalandharIndia
  2. 2.ECE DepartmentCT InstitutionsJalandharIndia

Personalised recommendations