Performance Enhancement of MRPSOC for Multimedia Applications

  • V. Kavitha
  • K. V. Ramakrishanan
Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 732)


There are several techniques to reconfigure the instruction set processors. One such technique is multi-reconfigurable instruction set processor system on chip (MRPSOC). Integration of MRPSOC and multigrain parallelism is done to improve the performance of SOC. By using MRPSOC, the performance of the system is increased. Multimedia application computing can be accelerated by using multigrain parallelism. By implementing this integrated processor, extra features can be added to MRPSOC. Multiple data is packed in a single register which forms a vector; this vector of multiple data is fetched to MRPSOC at a time. Since MRPSOC is a combination of MPSOC and RISP processor, instruction-level parallelism can be implemented in MRPSOC. After the execution of operations in MRPSOC, the multiple outputs can be stored at different memory locations of same memory system simultaneously. This proposal is aimed to design MRPSOC interfaced with data-level parallelism, instruction-level parallelism, and memory transfer-level parallelism. Form this paper, it is concluded that by using both MRPSOC and multigrain parallelism in common platform, high-speed computation can be achieved for multimedia applications. Proposed design takes 28% less time to complete the task compared to MPSOC. Further completion time will be reduced for tasks having repetitive instructions.


Reconfigurable instruction set processors (RISPs) Multigrain parallelism Multi-reconfigurable instruction set processor system on chip (MRPSOC) 


  1. 1.
    Soleymanpour, R., Mohammadi, S.: A platform for multi reconfigurable instruction set processor system on chip. In: CSI International Symposium, 2013, pp. 99–104Google Scholar
  2. 2.
    Huang, X., Fan, X., Zhang S., Shi L.: Investigation on multi-grain parallelism in chip multiprocessor for multimedia application. In: Proceeding of IEEE 2009, Computer School, Northwestern Polytechnical University, China (2009) Google Scholar
  3. 3.
    Kuroda, I., Nishitani, T.: Multimedia processors. Proc. IEEE 86(6), 1203–1221 (1998)CrossRefGoogle Scholar
  4. 4.
    Barat, F., Lauwereins, R.: Reconfigurable instruction set processors: a survey. Rapid System Prototyping, 11th International Workshop, pp. 168–173 (2000)Google Scholar
  5. 5.
    Pozzi, L., Atasu, K., Ienne, P.: Exact and approximate algorithms for the extension of embedded processor instruction sets. IEEE Trans. Comput. Aided Design Integr. Circ. Syst. 25(7), 1209–1229 (2006)CrossRefGoogle Scholar
  6. 6.
    Huang, X., Fan, X., Zhang S.: The integration of multimedia process unit into an embedded processor. In: Proceeding of the 2007 IEEE International Conference on Integration Technology, pp. 492–495, China, March 2007Google Scholar
  7. 7.
    Lo, J.L., Eggers, S.J.: Improving balanced scheduling with compiler optimization that increase instruction level parallelism. Department of Computer Science and Engineering, University of Washington (1995)Google Scholar
  8. 8.
    Lodi, A., Toma, M., Campi, F., Cappelli, A., Canegallo, R., Guerrieri, R.: A VLIW processor with reconfigurable instruction set for embedded applications. IEEE J. Solid-State Circ. 38(11), 1876–1886 (2003)CrossRefGoogle Scholar
  9. 9.
    Keutzer, K., Malik, S., Newton, A.R.: From ASIC to ASIP: the next design discontinuity (2002)Google Scholar
  10. 10.
    Qasim, Y., Janga, P., Kumar, S., Alesaimi, H.: Application specific processors. Final_ECE570_ASP_2012, Project Report (2012)Google Scholar
  11. 11.
    Nohl, A., Schirrmeister, F., Jaussig, D.: Application specific processor design: architecture, design methods and tools. In: 2010 IEEE/ACM International conference on Computer_Aided Design (ICCAD), November 2010Google Scholar
  12. 12.
    Wolf, W., Jerraya, A.A., Martin, G.: Multiprocessor system on chip (MPSOC) technology. IEEE Trans. Comput. Aided Design Integr. Circ. Syst. 27(10), 1701–1713 (2008)CrossRefGoogle Scholar
  13. 13.
    Asokan, P.: A novel MRPSOC processor for dispatch time curtailment, Final Report (2014)CrossRefGoogle Scholar
  14. 14.
    Grotker, T., Lio, S., Martin, G.: System design with system C. Kluwer Academic Publications (2002)Google Scholar

Copyright information

© Springer Nature Singapore Pte Ltd. 2018

Authors and Affiliations

  1. 1.Jain UniversityBengaluruIndia

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