Performance Enhancement of MRPSOC for Multimedia Applications

Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 732)

Abstract

There are several techniques to reconfigure the instruction set processors. One such technique is multi-reconfigurable instruction set processor system on chip (MRPSOC). Integration of MRPSOC and multigrain parallelism is done to improve the performance of SOC. By using MRPSOC, the performance of the system is increased. Multimedia application computing can be accelerated by using multigrain parallelism. By implementing this integrated processor, extra features can be added to MRPSOC. Multiple data is packed in a single register which forms a vector; this vector of multiple data is fetched to MRPSOC at a time. Since MRPSOC is a combination of MPSOC and RISP processor, instruction-level parallelism can be implemented in MRPSOC. After the execution of operations in MRPSOC, the multiple outputs can be stored at different memory locations of same memory system simultaneously. This proposal is aimed to design MRPSOC interfaced with data-level parallelism, instruction-level parallelism, and memory transfer-level parallelism. Form this paper, it is concluded that by using both MRPSOC and multigrain parallelism in common platform, high-speed computation can be achieved for multimedia applications. Proposed design takes 28% less time to complete the task compared to MPSOC. Further completion time will be reduced for tasks having repetitive instructions.

Keywords

Reconfigurable instruction set processors (RISPs) Multigrain parallelism Multi-reconfigurable instruction set processor system on chip (MRPSOC) 

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Copyright information

© Springer Nature Singapore Pte Ltd. 2018

Authors and Affiliations

  1. 1.Jain UniversityBengaluruIndia

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