Different Configuration of Low-Power Memory Design Using Capacitance Scaling on 28-nm Field-Programmable Gate Array

  • Inderpreet Kaur
  • Lakshay Rohilla
  • Alisha Nagpal
  • Bishwajeet Pandey
  • Sanchit Sharma
Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 732)

Abstract

A real capacitor will have some power dissipation, whereas an ideal capacitor will not dissipate any power. In this paper, we designed a capacitance scaling-based low-power RAM design. Our work aims to analyze how the memory circuit works using capacitance scaling does and varying temperatures. This design is implemented in Verilog. Usually, for the functioning of a device, the junction temperature is below 125 °C. If we scale down frequency from 10 to 4.5 GHz, 2.3 and 1 GHz then there is 42.96, 59.03, and 70.4% reduction, respectively, in total power at 5 pF output load. With the increase in capacitance, there should be the increase in junction temperature. But the novelty of our work is that we can control the effect of capacitance scaling on junction temperature with the help of addition airflow of 500 Linear Feet per Minute (LFM).

Keywords

I/O standard Thermal analysis SSTL135 Power optimized design I/Os power FPGA C = centigrade 

References

  1. 1.
    Garg, K., Moudgil, A., Das, B., Abdullah, M.F.L., Pandey, B., Akbar Hussain, D.M.: GTL based internet of things enable processor specific RAM design on 65 nm FPGA. In: IEEE 57th International Symposium ELMAR-2015, 28–30 Sept 2015, Zadar, Croatia: the oldest conference in EuropeGoogle Scholar
  2. 2.
    Verma, G., Moudgil, A., Garg, K., Pandey, B.: Thermal and power-aware internet of things enable RAM design on FPGA. In: IEEE International Conference on Computing for Sustainable Global Development (INDIACOM), Bharti Vidyapeeth, Delhi, India, Mar 2015. http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=7100506
  3. 3.
    Pandey, B., Singh, D., Pattanaik, M.: IO standard based low power design of RAM and implementation on FPGA. In: International Conference on Information Applied Electronics (ICIAE), Colombo, Sri Lanka, 15–16 June 2013. http://www.joace.org/uploadfile/2013/0705/20130705030847941.pdf
  4. 4.
    Dabbas, S., Pandey, B., Kumar, T., Das, T.: Design of power optimized memory circuit using high speed transreceiver logic IO standard on 28 nm field programmable gate array. In: IEEE International Conference on Reliability Optimization & Information Technology (ICROIT), Faridabad, India, Feb 2014Google Scholar
  5. 5.
    Tessier, R., et al.: Power-aware RAM mapping for FPGA embedded memory blocks. In: Proceedings of the 2006 ACM/SIGDA 14th International Symposium on Field programmable gate arrays. ACM (2006)Google Scholar
  6. 6.
    Chowdhry, B.S., Pandey, B., Kumar, T., Das, T., Thakur, S.: Frequency, voltage and temperature sensor design for fire detection in VLSI circuit on FPGA. In: Communications in Computer and Information Science, Indexed by Elsevier: SCOPUS. ISSN: 1865-0929Google Scholar

Copyright information

© Springer Nature Singapore Pte Ltd. 2018

Authors and Affiliations

  • Inderpreet Kaur
    • 1
  • Lakshay Rohilla
    • 1
  • Alisha Nagpal
    • 1
  • Bishwajeet Pandey
    • 1
  • Sanchit Sharma
    • 2
  1. 1.Department of Electronics and CommunicationsChitkara UniversityChandigarhIndia
  2. 2.Chandigarh College of Engineering and TechnologyChandigarhIndia

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