Input–Output Standard-Based Energy Efficient UART Design on 90 nm FPGA

  • Rashmi Sharma
  • Bishwajeet Pandey
  • Vikas Jha
  • Siddharth Saurabh
  • Sweety Dabas
Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 732)

Abstract

This paper illustrates the behavior of the UART in response to the various I/O standards. Research has been carried out to find out the most ideal standard for UART design which would thereby minimize the losses. Increase in power is seen as the frequency and capacitance for a standard are increased. When a relative analysis is done for the different I/O standards, it has been found out that LVCMOS18 consumes the least power and hence is the most efficient I/O standard for the UART design. Increment in power consumption has been observed within a percentage of 99.73–40% for a capacitance of 5 pF and 99.64–54.54% for a capacitance value of 50 pF. XILINX software and Verilog Hardware Description Language have been used for this purpose. The behavior for various standards has been studied to get the most energy-efficient design for the UART. This would help in increasing the output from the UART, thereby proving to be a boon in the field of electronics where power consumption is a major issue.

Keywords

Input Output Standard Energy efficient UART 90 nm FPGA 

References

  1. 1.
    Goswami, K., Pandey, B.: Energy efficient vedic multiplier design using LVCMOS and HSTL IO standard. In: 9th International Conference on Industrial and Information Systems (ICIIS), Dec 2014, pp. 1–4, 15–17Google Scholar
  2. 2.
    Pandey, B., Yadav, J., Pattanaik, M.: IO standard based energy efficient ALU design and implementation on 28 nm FPGA. 2013 Annual IEEE India Conference (INDICON). IEEE (2013)Google Scholar
  3. 3.
    Singh, P.R., et al.: I/O standard based power optimized processor register design on ultrascale FPGA. 2014 International Conference on Computing for Sustainable Global Development (INDIACom). IEEE (2014)Google Scholar
  4. 4.
    Kumar, T., et al.: Simulation of voltage based efficient fire sensor on FPGA using SSTL IO standards. In: 2014 International Conference on Robotics and Emerging Allied Technologies in Engineering (iCREATE). IEEE (2014)Google Scholar
  5. 5.
    Das, T., et al.: Simulation of SSTL IO standard based power optimized parallel integrator design on FPGA. In: 2014 International Conference on Robotics and Emerging Allied Technologies in Engineering (iCREATE). IEEE (2014)Google Scholar
  6. 6.
    Pandey, B., et al.: IO standard based green multiplexer design and implementation on FPGA. In: 2013 5th International Conference on Computational Intelligence and Communication Networks (CICN). IEEE (2013)Google Scholar
  7. 7.
    Singh, P.R., et al.: Output load capacitance based low power implementation of UART on FPGA. In: 2014 International Conference on Computer Communication and Informatics (ICCCI). IEEE (2014)Google Scholar

Copyright information

© Springer Nature Singapore Pte Ltd. 2018

Authors and Affiliations

  • Rashmi Sharma
    • 1
  • Bishwajeet Pandey
    • 1
  • Vikas Jha
    • 1
  • Siddharth Saurabh
    • 2
  • Sweety Dabas
    • 3
  1. 1.Gyancity Research LabGurgaonIndia
  2. 2.Giant Meterwave Radio TelescopeKhodad, PuneIndia
  3. 3.Maharaja Surajmal InstituteJanakpuriIndia

Personalised recommendations