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Timing Constraints-Based High-Performance DES Design and Implementation on 28-nm FPGA

  • Vandana Thind
  • Sujeet Pandey
  • D. M. Akbar Hussain
  • Bhagwan Das
  • M. F. L. Abdullah
  • Bishwajeet Pandey
Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 732)

Abstract

In this work, we are going to implement DES algorithm on 28-nm Artix-7 FPGA. To achieve high-performance design goal, we are using minimum period, maximum frequency, minimum low pulse, minimum high pulse for different cases of worst-case slack, maximum delay, setup time, hold time, and data skew path. The cases on which analysis is done are like worst-case slack, best-case achievable, timing error, and timing score, which help in differentiating the amount of timing constraint at two different frequencies. We analyzed that in timing analysis, there is maximum of 19.56% of variation in worst-case slack, 0.29% change for best-case achievable, 41.17% change in timing error, and 64.12% change in timing score for two different frequencies. From this work, we also notified the delays during various signals; accordingly, we have designed our own algorithm with strong security encryption.

Keywords

Timing constraints DES algorithm 28-nm FPGA Pin-out report Mapping report Minimum period Maximum performance Static timing analysis 

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Copyright information

© Springer Nature Singapore Pte Ltd. 2018

Authors and Affiliations

  • Vandana Thind
    • 1
  • Sujeet Pandey
    • 2
  • D. M. Akbar Hussain
    • 3
  • Bhagwan Das
    • 4
  • M. F. L. Abdullah
    • 4
  • Bishwajeet Pandey
    • 2
  1. 1.School of Electronics and ElectricalChitkara UniversityChandigarhIndia
  2. 2.Gyancity Research LabJammuIndia
  3. 3.Aalborg UniversityEsbjergDenmark
  4. 4.UTHMParit RajaMalaysia

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