LVCMOS-Based Low-Power Thermal-Aware Energy-Proficient Vedic Multiplier Design on Different FPGAs

  • Arushi Aggarwal
  • Bishwajeet Pandey
  • Sweety Dabbas
  • Achal Agarwal
  • Siddharth Saurabh
Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 732)


In the paper, we’ll be discussing about amalgamating thermal-aware intent in energy-proficient Vedic multiplier on different FPGAs. LVCMOS is a contraction for low-voltage complementary metal-oxide semiconductor. Here, we are implementing this Vedic multiplier design via three LVCMOS I/O standards they are: LVCMOS12, LVCMOS18, and LVCMOS25 which are accessible among 45, 40, and 28-nm FPGA. To check the thermal-aware of our design on the Vedic multiplier, we are analyzing the design at diverse room temperatures 20, 30, and 45 °C. Vedic Mathematics is one of the oldest processes of arithmetic that has a distinctive method of performing a calculation based on different Sutras. The techniques showed in this paper is Yavadunam Tavadunikrtya, and the recital study of these techniques is obtained as: for LVCMOS_18, as the multiplier design is migrated from 45 to 28-nm intent, there is 88.29% diminution in Leakage control of Vedic multiplier at constant temperature of 20 °C, for LVCMOS_15, as the Vedic multiplier intent is moved from 45 to 90-nm intent, there is 89.54% diminution in Leakage control of Vedic multiplier at constant temperature of 30 °C.


Thermal-aware design Multiplier Yavadunam Tavadunikrtya LVCMOS Energy efficient design IO standards 


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Copyright information

© Springer Nature Singapore Pte Ltd. 2018

Authors and Affiliations

  • Arushi Aggarwal
    • 1
  • Bishwajeet Pandey
    • 1
  • Sweety Dabbas
    • 1
  • Achal Agarwal
    • 2
  • Siddharth Saurabh
    • 3
  1. 1.Gyancity Research LabGurugramIndia
  2. 2.Ajay Kumar Garg Engineering CollegeGhaziabadIndia
  3. 3.Giant Meterwave Radio TelescopeKhodad, PuneIndia

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