Abstract
Performance of multipliers has a tremendous impact on system-level functionality especially in signal processing and image processing applications. In this short, the sum-of-power-of-two (SOPOT)-based multiplier is investigated and from this investigation some unnecessary shifters and multiplexers are observed. The unnecessary shifters and multiplexers exist in SOPOT architecture are eliminated and a novel multiplier is proposed using canonical-signed digit (CSD) representation and also the size of control register is reduced. The modified architecture is superior to the existing architecture as there is a reduction in area and power consumption. The lifting scheme discrete wavelet transform has been implemented using modified multiplier. The synthesis results show the modified CSD architecture area delay product (ADP) and energy are less than the previous design respectively.
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Kishore Kumar, G., Balaji, N. (2018). Implementation of Lifting Scheme Discrete Wavelet Transform Using Modified Multiplier. In: Bhattacharyya, S., Gandhi, T., Sharma, K., Dutta, P. (eds) Advanced Computational and Communication Paradigms. Lecture Notes in Electrical Engineering, vol 475. Springer, Singapore. https://doi.org/10.1007/978-981-10-8240-5_38
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DOI: https://doi.org/10.1007/978-981-10-8240-5_38
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