Abstract
When the technology of VLSI circuits scales down to nanometer region, the parameter variation has a great impact on the circuit performance. Traditional false path filtering methods which use normal corner-based timing analysis miss some of the critical false paths or true paths. Viability analysis is one of the most accurate methods for false path filtering. Statistical timing analysis, which models the parameter variation statistically, becomes a promising variation-aware solution in the digital circuit design at the nanometer era. Thus, statistical viability analysis improves the accuracy in finding false paths or true paths in a design. For further optimization, the concept of gate sizing is used along with viability analysis. The criticality for gate selection is evaluated through viability analysis. The analysis and optimization are carried out on ISCAS 85 benchmark circuits. For a sample circuit C2670, a delay reduction of 10.99% is obtained with a slight increase in power of 0.65% and area overhead of 0.63%.
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Sreenath, K., Ramesh, S.R. (2018). Statistical Viability Analysis and Optimization Through Gate Sizing. In: Bhattacharyya, S., Gandhi, T., Sharma, K., Dutta, P. (eds) Advanced Computational and Communication Paradigms. Lecture Notes in Electrical Engineering, vol 475. Springer, Singapore. https://doi.org/10.1007/978-981-10-8240-5_17
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DOI: https://doi.org/10.1007/978-981-10-8240-5_17
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