Implementation of Non-restoring Reversible Divider Using a Quantum-Dot Cellular Automata

  • Ritesh Singh
  • Neeraj Kumar MisraEmail author
  • Bandan Bhoi
Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 711)


The CMOS-based integrated circuit may scale down to nanometer range. The primary challenge is to further downscale the device and high-energy dissipation. Reversible logic does not dissipate energy and no information loss. In this way, the state-of-the-art technology such as QCA was forced toward high-speed computing with negligible energy dissipation in the physical foreground. This work targets the design of non-restoring reversible divider circuit and its implementation in QCA. We have utilized few 2 × 2 FG and 4 × 4 HNG gates as the block construction and also show the QCA implementation having cost-efficient approach. Further, the divider circuit has synthesized with FG and HNG gates and QCA implementation. This divider circuit inherits many benefits such as fewer garbage outputs, reduce quantum cost are achieved, and also reduced QCA primitives can be improved by using efficient QCA layout scheme. Simulation investigations have been verified by QCA Designer. The proposed non-restoring divider also compares the reversible metrics results with some of other existing works.


Quantum-dot cellular automata Nanoelectronics Clocking Reversible computing High-speed nanoelectronics 


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Copyright information

© Springer Nature Singapore Pte Ltd. 2019

Authors and Affiliations

  • Ritesh Singh
    • 1
  • Neeraj Kumar Misra
    • 1
    • 2
    Email author
  • Bandan Bhoi
    • 3
  1. 1.Department of Electronics EngineeringInstitute of Engineering and TechnologyLucknowIndia
  2. 2.Department of Electronics and Communication EngineeringBharat Institute of Engineering and TechnologyHyderabadIndia
  3. 3.Departement of Electronics and TelecommunicationVeer Surendra Sai University of TechnologyBurlaIndia

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