Abstract
Recent IC technology emphases on the fabrication of ICs as more area optimization and low-power practices. Among all the arithmetic operations, the most heavily used one is multiplication that measures more frequently in signal processing applications. Multiplication is a very hardware-focused subject, and we as customers are mostly worried with getting low power, smaller area, and higher speed. The most important concern in classic multiplication mostly realized by shifting and adding is to accelerate fundamental multi-operand addition of partial products. In this literature, the Booth multiplier implementation is presented with different adder architectures like ripple carry adder and carry look ahead adder and carry select adder. The time delay, area, and power have been investigated for different adders.
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Sarkar, U., Nath, R., Das, S. (2018). VLSI Implementation of Booth’s Multiplier Using Different Adders. In: Bera, R., Sarkar, S., Chakraborty, S. (eds) Advances in Communication, Devices and Networking. Lecture Notes in Electrical Engineering, vol 462. Springer, Singapore. https://doi.org/10.1007/978-981-10-7901-6_7
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DOI: https://doi.org/10.1007/978-981-10-7901-6_7
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