Implementation of High-Performance Floating Point Divider Using Pipeline Architecture on FPGA

  • C. R. S. Hanuman
  • J. Kamala
Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 695)


Data intensive DSP algorithms mostly depend on double precision (DP) floating point arithmetic operations. With advanced FPGA devices, applications need more floating point arithmetic operations to accelerate reconfigurable logic. Important and complex applications heavily depend on the floating point divider (FPD) blocks. This paper illustrates implementation of low-latency dividers based on pipelining, which is operated at 30% faster than existing divider. DPFPD implemented using field programmable gate array (FPGA) outperforms other ULP dividers. Pipelining architecture of FPD increases the throughput and reduces the power considerably. The architecture is validated for standalone as well as integrated application levels.


ULP Reconfigurable logic DPFPD FPGA 


  1. 1.
    Wang, L.-K., Schulte, M.J.: A decimal floating point divider using newton-raphson iteration. The J. VLSI Signal Process. 49(1), 3–18 (2007) (Springer, USA)CrossRefGoogle Scholar
  2. 2.
    Amanollahi, S., Jaberipur, G.: Energy efficient VLSI realization of binary 64 division with redundant number systems. In: IEEE Transactions on Very Large Scale Integration systems, pp. 1–12 (June 2016)Google Scholar
  3. 3.
    Muller, Jean-Michel, Functions, Elementary: Algorithms and Implementation. Birkhauser Boston Publishers, Springer science (2016)Google Scholar
  4. 4.
    Govindu, G., Scrofano, R., Prasannna, V.K.: A library of parameterizable floating point cores for FPGAs and their application to scientific computing. In: International Conference on Engineering of Reconfigurable Systems and Algorithms (2005)Google Scholar
  5. 5.
    Wei, L., Nannarelli, Alberto: Power efficient division and square root unit. IEEE Trans. Comput. 61(8), 1059–1070 (2012)MathSciNetCrossRefGoogle Scholar
  6. 6.
    Hemmert, K.S., Underwood, K.D.: Floating point divider design for FPGAs. In: IEEE Transaction on very large scale integration systems, vol. 15, No. 1, pp. 115–118, (Jan 2007) (K. Elissa)CrossRefGoogle Scholar
  7. 7.
    Wang, X., Nelson, B.E.: Tradeoffs of designing floating point division and square root on virtex FPGAs. In: International Conference on Engineering of Reconfigurable Systems and Algorithms (2004)Google Scholar
  8. 8.
    Jaiswal, M.K., Cheung, R.C.C., Balakrishnan, M., Paul, K.: Series expansion based efficient architectures for double precision floating point division. J. Circuits, Syst. Signal Process. 33(11), 3499–3526 (2014) (Springer)CrossRefGoogle Scholar
  9. 9.
    Soderquist, Peter, Leeser, Miriam: Division and square root: choosing the right implementation. IEEE Micro 17(4), 56–66 (1997)CrossRefGoogle Scholar
  10. 10.
    Paschalakis, S., Lee, P.: Double precision floating point arithmetic on FPGAs. In: IEEE Conference on Field Programmable Technology (2003)Google Scholar
  11. 11.
    Oberman, S.F., Flynn, M.J.: Division algorithms and implementations. IEEE Trans. Comput. 46(8), 833–854 (1997)MathSciNetCrossRefGoogle Scholar

Copyright information

© Springer Nature Singapore Pte Ltd. 2018

Authors and Affiliations

  1. 1.Department of Electronics and Communication EngineeringCollege of Engineering, Guindy, Anna UniversityChennaiIndia

Personalised recommendations