Abstract
The messages in the latest security protocols such as IPSec, TLS and SSL must be handled by high-speed crypto systems. Current computationally extensive cryptographic implementations on different platforms such as software, Application Specific Integrated Circuit (ASIC) and Field Programmable Gate Array (FPGA) without adequate optimization achieve lesser throughput than should be possible. In the paper we consider a cryptographic hashing algorithm KECCAK and its implementations. To achieve better throughput, the proposed implementations of KECCAK explores FPGA design spaces. In this paper three different architectures for KECCAK coprocessor are implemented in Artix-7 (XC7A100T, CSG324) FPGA platform. The Processing Element (PE) handles all communication interfaces, data paths and control signals hazards of Network Security Processor (NSP). A partitioned area in the system ensures that the processor data path is completely isolated from secret key memory. The memory to KECCAK core communication is done by Direct Memory Access Controller (DMA). The performances of the implemented KECCAK are better in terms of throughput and resource usage than the existing work reported in the literature.
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Paul, R., Shukla, S.K. (2017). A High Speed KECCAK Coprocessor for Partitioned NSP Architecture on FPGA Platform. In: Kaushik, B., Dasgupta, S., Singh, V. (eds) VLSI Design and Test. VDAT 2017. Communications in Computer and Information Science, vol 711. Springer, Singapore. https://doi.org/10.1007/978-981-10-7470-7_50
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DOI: https://doi.org/10.1007/978-981-10-7470-7_50
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