Comparison of Logic Built-in-Self Test Techniques Based on FPGA in Verilog

Conference paper
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 472)


Logic built-in self test (BIST) is the part of the circuit, dedicated to test the given circuit for correctness of its operation. In this paper, different techniques of test pattern generation, the first element of BIST, have been compared based on the critical parameters of delay, power consumption and hardware utilization. The random patterns are generated for International Symposium on Circuits and Systems’ (ISCAS) benchmark circuit using linear feedback shift register (LFSR). The device used for hardware implementation is Spartan 2E—xc2s50e-7ft256 in Xilinx ISE. Simulation results are obtained in ModelSim 5.4, and power consumption analysis is done using XPower analyzer in Xilinx. The fault coverage results are obtained in MATLAB to grade the test patterns for their testing efficiency. The detailed analysis of the results and the corresponding plots are provided in support of our argument.


Fault modelling Output response analyzers Cellular automata Gray counter Fault coverage 


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Copyright information

© Springer Nature Singapore Pte Ltd. 2018

Authors and Affiliations

  1. 1.Government Engineering College BharatpurBharatpurIndia
  2. 2.MNITJaipurIndia

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