Bat Algorithm Based Low Power Mapping Methods for 3D Network-on-Chips
Mapping a task graph as a distribution of Intellectual Property (IP) cores onto a Network-on-Chip (NoC) is a NP-hard problem that significantly affects the performance metrics of the whole system including power, delay, load balance and heat. Intelligence optimization algorithms are widely used to solve mapping problems. Bat Algorithm (BA), a novel metaheuristic algorithm mimicking hunting behaviors of bats, which has never been applied in NoCs, is used in low power mapping methods for 3D NoCs in this paper for the first time. The BA based mapping algorithm shows better performance than other mainstream mapping algorithms in terms of the optimization efficiency and power consumption. However, the concept of the basic BA has obvious disadvantages. To improve the basic BA, we propose a Group-Searching Bat Algorithm (GSBA) that can better utilize individual bats. This improved mapping algorithm performs much better than the traditional BA, especially when the scale of the application graph is large.
KeywordsNetwork-on-Chip Mapping algorithm Low power Bat Algorithm Parallel computing
The authors were support by National Training Program of Innovation and Entrepreneurship for Undergraduates No. 201710058042 and 201710058009. We thank the anonymous reviewers for commenting on this paper.
- 2.Ogras, U.Y., Hu, J., Marculescu, R.: Key research problems in NoC design: a holistic perspective. In: Proceedings of CODES+ISSS, Jersey City, NJ, pp. 69–74, September 2005Google Scholar
- 4.Huang, C., Zhang, D.K., Song, G.Z.: Survey on mapping algorithm of three-dimensional network on chip. J. Chin. Comput. Syst. 37(2), 193–201 (2016)Google Scholar
- 8.Wang, G.G., Guo, L.H., Duan, H., Liu, L., Wang, H.Q.: A bat algorithm with mutation for UCAV path planning. Sci. World J. (2012). Article ID 418946Google Scholar
- 11.Tangherloni, A., Nobile, M.S., Cazzaniga, P.: GPU-powered bat algorithm for the parameter estimation of biochemical kinetic values. In: IEEE International Conference on Computational Intelligence in Bioinformatics and Computational Biology (CIBCB 2016), Chiang Mai, Thailand, October 2016Google Scholar
- 13.Black, B., Annavaram, M., Brekelbaum, N., DeVale, J., Jiang, L., Loh, G.H. et al.: Die stacking (3D) microarchitecture. In: IEEE/ACM International Symposium on Microarchitecture, pp. 469–479. IEEE Xplore (2006)Google Scholar
- 14.Addo-Quaye, C.: Thermal-aware mapping and placement for 3-D NoC designs. In: Proceedings of IEEE International SOC Conference, pp. 25–28. IEEE Xplore (2005)Google Scholar
- 15.Yang, W., Zhang, Z., Liu, Y.J.: Improved particle swarm optimization algorithm based mapping algorithm for 3D-Mesh CMP. Appl. Res. Comput. 30(5), 1345–1348 (2013)Google Scholar
- 16.Jheng, K.Y., Chao, C.H., Wang, H.Y., Wu, A.Y.: Traffic-thermal mutual-coupling co-simulation platform for three-dimensional network-on-chip. In: International Symposium on VLSI Design Automation and Test, vol. 54, pp. 135–138. IEEE Explore (2010)Google Scholar
- 17.Fister, Jr., I., Fong, S., Brest, J., Fister, I.: A novel hybrid self-adaptive bat algorithm. Sci. World J. (2014). Article ID 709738Google Scholar
- 19.Xue, F.: Research and application of heuristic intelligence optimization based on bat algorithm. Doctoral Dissertation, Beijing University of Technology (2016)Google Scholar
- 20.Dick, R.P., Rhodes, D.L., Wolf, W.: TGFF: task graphs for free. In: Proceedings of the Sixth IEEE International Workshop on Hardware/Software Codesign (CODES/CASHE 1998), pp. 97–101 (1998)Google Scholar
- 21.Tornero, R., Sterrantino, V., Palesi, M., Orduna, J.M.: A multi-objective strategy for concurrent mapping and routing in networks on chip. In: IEEE International Symposium on Parallel and Distributed Processing (IPDPS), Rome, Italy, May. 2009Google Scholar