Abstract
This paper presents a fault-tolerant topology reconfiguration backtracking algorithm to tolerate faulty cores in 2D REmesh based (reconfigurable mesh based) Networks-on-Chip. This new algorithm can be dynamically reconfigured to support irregular topologies caused by faulty cores in a REmesh network without destroying the integrity of topologies. In addition, the proposed reconfigure method has a high-level fault-tolerance capability and therefore it is capable to tolerate more faulty components in more complicated faulty situations without additional hardware costs. The reliability performance and fault-tolerance capability of the reconfiguration backtracking algorithm in a 2D REmesh network are evaluated through appropriate simulations. The experimental results show that in different sizes of topologies (the max size is 7 × 8), when less than 10.7% faulty cores occur, more than 91.5% successful reconfiguration rate can be achieved. In addition, in the 7 × 8 REmesh, when the faulty core reaches 7, the successful reconfiguration rate has reached 61.49%, which enhanced 9.74% compared with the TRARE algorithm.
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Acknowledgement
This work is supported by a grant from National Natural Science Foundation of China (NSFC, No.61504032).
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Niu, N., Fu, FF., Li, H., Lai, FC., Wang, JX. (2017). A Novel Topology Reconfiguration Backtracking Algorithm for 2D REmesh Networks-on-Chip. In: Chen, G., Shen, H., Chen, M. (eds) Parallel Architecture, Algorithm and Programming. PAAP 2017. Communications in Computer and Information Science, vol 729. Springer, Singapore. https://doi.org/10.1007/978-981-10-6442-5_5
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DOI: https://doi.org/10.1007/978-981-10-6442-5_5
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