Design of Novel Through Silicon via Structures for Reduced Crosstalk Effects in 3D IC Applications
In recent days, through silicon via (TSV) become a promising technology for integrated circuit packaging. The structure of the TSV composed of copper, insulating liner, and silicon substrate. The TSV is enclosed using insulating liner to troubleshoot the leakage in signal from copper (Cu) to silicon (Si) substrate. In the existing TSV structures, silicon dioxide (SiO2) dielectric is used as insulation liner because of its material compatibility with the silicon substrate. On the other hand, several researchers were reported the problems of SiO2. Due to the high dielectric constant of SiO2, the insulating capacitance increases that result in increasing of delay. Therefore, SiO2 is not suitable for high-performance applications. To alleviate the insulating capacitance, polymer liner is used rather than SiO2. A proposed novel TSV structure consists of the signal TSV is encompassed by utilizing the poly-propylene liner. For comparison purpose, we perform the simulations for both conventional and proposed TSV structures by varying different design parameters of TSV. It has been observed that the proposed TSV structure shows 25% decrease in crosstalk compared to conventional TSV structures.
KeywordsThrough Silicon Via (TSV) Poly-propylene liner Polymer capacitance Crosstalk
The authors would like to thank Science and Engineering Research Board (SERB), DST, Government of India for the financial support of the project file number ECR/2016/001070.
- 1.DC Yang, J. Xie, and M. Swaminathan, “A Rigorous Model for Through-Silicon Vias With Ohmic Contact in Silicon Interposer,” IEEE microwave and wireless components letters., vol. 23, no. 8, pp. 385–387, July 2013.Google Scholar
- 2.B. K. Kaushik, M. K. Majumder, and V. Ramesh Kumar, “Carbon nanotube based 3-D interconnects - A reality or a distant dream,” IEEE Circuits and Systems Magazine, vol. 14, no. 4, pp. 16–35, Nov. 2014.Google Scholar
- 3.V. Ramesh Kumar, M. K. Majumder, and B. K. Kaushik, “Graphene based on-chip interconnects and TSVs – Prospects and challenges,” IEEE Nanotechnology Magazine, vol. 8, no. 4, pp. 14–20, Nov. 2014.Google Scholar
- 4.M. K. Majumder, A. Kumari, A. Alam, V. Ramesh Kumar, and B. K. Kaushik, “Signal integrity improvement with peripherally placed MWCNTs in mixed CNT bundle based TSVs,” in Proc. IEEE Conference on Electron Devices and Solid-State Circuits, Singapore, pp. 649–652, June, 2015.Google Scholar
- 5.G. Katti, M. Stucchi, K. De Meyer, and W. Dehaene, “Electrical modeling and characterization of through silicon via for three-dimensional ICs,” IEEE Trans. Electron Devices, vol. 57, pp. 256–262, 2010.Google Scholar
- 6.T. Bandyopadhyay, K. J. Han, and D. Chung, “Rigorous electrical modeling of Through Silicon Vias (TSVs) with MOS capacitance effects,” IEEE Trans. Comp. Packag. Manufact. Technol., vol. 1, pp. 893–903, 2011.Google Scholar
- 7.E. Engin and N. S. Raghavan, “Metal semiconductor (MES) TSVs in 3D ICs: Electrical modeling and design,” in Proc. IEEE Int. 3D Syst. Integr. Conf., 2012, pp. 1–4.Google Scholar
- 8.B. K. Kaushik, V. Ramesh Kumar, M. K. Majumder, and A. Alam “Through Silicon Vias – Materials, Models, Design and Performance,” CRC Press, Taylor & Francis, 2016.Google Scholar