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Line-Based Successive Cancellation Decoder with Reduced Complexity

  • G. M. G. Madhuri
  • B. Praveen Kitti
  • N. Prasanthi Kumari
Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 624)

Abstract

The error-correcting codes which achieve Shannon’s channel capacity are polar codes for infinite length. In this, we propose an efficient implementation for SC polar decoders with O(log2N) processing elements, where N is code block length. Here, SC decoding processing unit is implemented in logarithmic domain, thereby reducing the multiplication and division operations and low-complex partial sum logic. This decoder architecture has a low dispensation density that allows large polar codes to put into practice. Simulation is done using Xilinx, and simulation results are presented.

Keywords

Successive cancellation decoder VLSI Polar codes Partial sum logic 

References

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Copyright information

© Springer Nature Singapore Pte Ltd. 2018

Authors and Affiliations

  • G. M. G. Madhuri
    • 1
  • B. Praveen Kitti
    • 1
  • N. Prasanthi Kumari
    • 2
  1. 1.PSCMR College of Engineering and TechnologyVijayawadaIndia
  2. 2.College of Engineering StudiesUniversity of Petroleum and Energy StudiesDehradunIndia

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