Low-Offset High-Speed CMOS Dynamic Voltage Comparator

  • Priyesh P. Gandhi
  • Niranjan M. Devashrayee
Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 624)


In this paper, authors have proposed low-offset high-speed voltage comparator which can be realized in A/D converters. It features low-offset and larger input swing at lower operating voltage. A comparison between typical comparator and the proposed comparator in 180 nm has been made. In the proposed comparator, the ICMR is considerably improved with reduction in offset voltage and power consumption. The power consumption of the proposed comparator is about 20% less as compared to conventional comparator, and its offset voltage is 28% less in comparison with other mentioned conventional comparators.


CMOS Dynamic comparator Offset Speed Analog-to-digital converters (ADCs) 


  1. 1.
    R. Jecob Baker, Harry W. Li, David E. Boyce, “CMOS Circuit Design, Layout and Simulation”, IEEE Press Series on Microelectronic Systems, 1997, pp. 685–699.Google Scholar
  2. 2.
    Phillip E. Allen, Douglas R. Holberg, “CMOS Analog Circuit Design”, Oxford University Press, Second Edition, 2002, pp. 439–488.Google Scholar
  3. 3.
    Vipul Katyal, Randall L. Geiger and Degang J. Chen, “A New High Precision Low Offset Dynamic Comparator for High Resolution High Speed ADCs”, IEEE Asia Pacific Conference on Circuits and Systems, 2006 (APCCAS 2006) pp. 5–8, Dec. 2006.Google Scholar
  4. 4.
    P. Uthaichana, E. Leelarasmee, “Low Power CMOS Dynamic Latch Comparators”, TENCON 2003, Conference on Convergent Technologies for the Asia-Pacific Region, pp 605–608 Vol. 2 Oct 2003.Google Scholar
  5. 5.
    HeungJun Jeon, Yong-Bin Kim, “A CMOS Low Power Low Offset and High-Speed Fully Dynamic Latched Comparator”, SOC Conference (SOCC), 2010 IEEE International, pp. 285–288, 2012.Google Scholar
  6. 6.
    M. Hassanpourghadi, M. Zamani and M. Sharifkhani, “A Low-Power Low-Offset Dynamic Comparator for Analog to Digital Converters”, Microelectronics Journal, 2013. pii/S0026269213002863 Elsevier, pp. 256–262. 2013.Google Scholar
  7. 7.
    Dhanisha N. Kapadia, Priyesh P. Gandhi “Design and Comparative Analysis of Differential Current Sensing Comparator in Deep Sub -Micron Region”. Proceedings of 2013 IEEE Conference on Information and Communication Technologies (ICT 2013).Google Scholar
  8. 8.
    Dhanisha N. Kapadia, Priyesh P. of CMOS Charge Sharing Dynamic Latch Comparator in 130 nm and 90 nm Technologies”. Proceedings of 2013 IEEE Conference on Information and Communication Technologies (ICT 2013).Google Scholar
  9. 9.
    L. Sumanen, M. Waltari, V. Hakkarainen, K. Halonen, “CMOS Dynamic Comparators for Pipeline A/D Converters,” IEEE ISCAS, vol. 5, pp. 157–160, May 2002.Google Scholar
  10. 10.
    T. W. Matthews, P. L. Heedley, “A Simulation Method for Accurately Determining DC and Dynamic Offset in Comparators,” IEEE MWSCAS, pp. 1815–1818, Aug. 2005.Google Scholar

Copyright information

© Springer Nature Singapore Pte Ltd. 2018

Authors and Affiliations

  1. 1.Nirma UniversityAhmedabadIndia

Personalised recommendations