FPGA Implementation of High Speed Multiplier with Optimized Reduction Phase

  • Arpita Singh
  • Abhay Sharma
  • Priyanka Kumari
Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 624)


Multipliers play an important role in DSP applications hence, the delay executed by them is a dominating factor. Various multiplication algorithms are used to enhance the speed of the device. All these multipliers are then compared based on look up table (LUTs) and path delays. The simulated results show that the Wallace tree multiplier is the fastest multiplier, and by using carry look-ahead adder (CLA) for addition, delay is further reduced.


Wallace tree multiplier Reduced partial products Carry look-ahead adder Delay LUTs 


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Copyright information

© Springer Nature Singapore Pte Ltd. 2018

Authors and Affiliations

  1. 1.Department of Electronics and Communication EngineeringGraphic Era UniversityDehradunIndia
  2. 2.Department of Electronics and Communication EngineeringGraphic Era Hill UniversityDehradunIndia

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