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Design of Power Efficient SRAM on FPGA

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Book cover Proceedings of the International Conference on Modern Research in Aerospace Engineering

Part of the book series: Lecture Notes in Mechanical Engineering ((LNME))

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Abstract

Low power based-Static RAM is designed using LVTTL and Mobile-DDR IO Standards on 28 nm Artix-7 FPGA. And at different range of operating frequency power dissipation has been calculated and amount of power dissipation by using LVTTL and Mobile-DDR IO buffer has been compared with each other, Mobile-DDR is more power efficient. At operating frequency of 1 GHz, 2 GHz, and 3 GHz, Mobile-DDR is used in place of LVTTL then 31.26%, 43.14%, and 47.45% total power can be saved, respectively.

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Authors and Affiliations

  1. Department of Electronics and Communication, G.L.A. University, Mathura, India

    Tarun Agrawal

Authors
  1. Tarun Agrawal
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Correspondence to Tarun Agrawal .

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Editors and Affiliations

  1. Amity Institute of Aerospace Engineering, Amity University, Noida, Uttar Pradesh, India

    Sanjay Singh

  2. DTC Secretariat, Ghaziabad, Uttar Pradesh, India

    Pushkar Raj

  3. Department of Aerospace Engineering and Engineering Mechanics, College of Engineering and Applied Sciences, University of Cincinnati, Cincinnati, Ohio, USA

    Samir Tambe

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Agrawal, T. (2018). Design of Power Efficient SRAM on FPGA. In: Singh, S., Raj, P., Tambe, S. (eds) Proceedings of the International Conference on Modern Research in Aerospace Engineering. Lecture Notes in Mechanical Engineering. Springer, Singapore. https://doi.org/10.1007/978-981-10-5849-3_35

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  • DOI: https://doi.org/10.1007/978-981-10-5849-3_35

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  • Publisher Name: Springer, Singapore

  • Print ISBN: 978-981-10-5848-6

  • Online ISBN: 978-981-10-5849-3

  • eBook Packages: EngineeringEngineering (R0)

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