Abstract
Carrier tracking phase lock loop (PLL) applied extensively in GNSS receivers and high-precision time transfer systems. The PLL is one of the important structures for carrier phase tracking in receivers. Generally, carrier phase noise can be degraded by local frequency references. However, this modification induces phase jitter, so that the accuracy of carrier phase in PLL will be reduced. On this basis, the characteristic of phase noise in carrier tracking is analyzed under the classic power law model and the variance of carrier phase jitter is calculated in the conventional second-order carrier PLL. Optimization is analyzed to obtain the optimal design of loop bandwidth, damping factor and coherent integration time (CIT) under the influence of phase noise in GNSS receivers. As a result, it is useful for carrier tracking to improve the performance of carrier PLL in the presence of phase noise and to reduce the variance of carrier phase jitter.
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Xue, S., Huang, X., Liu, Z., Zhu, X., Sun, G. (2017). Optimal Carrier Tracking PLL in the Presence of Phase Noise in GNSS Receiver. In: Sun, J., Liu, J., Yang, Y., Fan, S., Yu, W. (eds) China Satellite Navigation Conference (CSNC) 2017 Proceedings: Volume I. CSNC 2017. Lecture Notes in Electrical Engineering, vol 437. Springer, Singapore. https://doi.org/10.1007/978-981-10-4588-2_80
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DOI: https://doi.org/10.1007/978-981-10-4588-2_80
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