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Envisioning Post Domain of Restructured Accelerated Power Development and Reforms Programme-Fault Current Limiters

  • Jagdish Prasad Sharma
  • Vibhor Chauhan
Conference paper
Part of the Springer Proceedings in Energy book series (SPE)

Abstract

In the restructured environment, distributed generation (DG) can play an important role to maintain the expected voltage level, an improvement in network flexibility, sustainability, and reliability. The DG integration generally raises the fault level in many places, which may often exceed from withstanding capacity of present infrastructure. This increased fault level has the severe impact on power quality and voltage stability. Therefore, it is needed to operate existing network with the increased fault level constraint. With the Indian perspective of growing economy and increasing electricity demand, the fault current limiter (FCL) is a promising option to enhance the useful life of the equipments, even though fault current withstands capability has exceeded. These FCL have a modular design and easily customized as per constraints, system parameter, location choice, and space availability. A superconducting fault current limiter (SFCL) and solid-state fault current limiter (SSFCL) are two types of commercially available FCL solutions. At present, advancement in the high-temperature superconductor has reduced the cooling cost of SFCL, whereas high power switching development makes SSFCL more viable. There is a significant progress towards SFCL technologies across the global. To study various challenges and components of technology development for SFCL, a joint research project initiated by Crompton Greaves R&D and Ministry of Power, Government of India under the National Perspective Plan (NPP) project scheme. The focus of this paper is at describing how SSFCL may be considered for voltage sag mitigation and suppression of fault current for unsymmetrical/symmetrical faults on a parallel distribution feeder.

Keywords

Voltage sag mitigation Superconducting fault current limiter Solid-state fault current limiter Prospective fault current 

References

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Copyright information

© Springer Nature Singapore Pte Ltd. 2018

Authors and Affiliations

  1. 1.JK Lakshmipat UniversityJaipurIndia
  2. 2.Jaipur Institute of TechnologyJaipurIndia

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