Keywords

1 Introduction

VLSI is a method of making integrated circuits by combining countless transistors in an exceedingly single chip. In today’s era as the technology gets more advances, the number of devices organized on chips increased, leading to more number of interconnects [1]. These interconnect now not behave as simple resistors but can also have related parasitic consisting of capacitance and inductance, which leads to signal degradations. With growing need of transportable systems, low propagation delay and power dissipation are the major challenges for researchers. As the interconnect length increases linearly, the parasitic interconnect capacitance (C) and interconnect resistance (R) also increase linearly which in turn increase the RC product thereby increasing the propagation delay [2]. This is due to the linear increase in both the interconnect resistance and capacitance with increase of interconnect length. In the same way in deep submicron technologies also the propagation delay increases with increase in the parasitic and interconnects length.

Frequency of operation in the global interconnects is characterized by capacitive, resistive, and inductive properties which have more effect on the circuit performance [2]. In this paper, an attempt is to study the effects of these parasitic on circuit design parameters such as power, delay, and energy by considering different interconnect structures such as single interconnect and coupled interconnects for copper wire with simple CMOS driver and load. Different technologies along with different lengths of interconnects have been considered and calculated the propagation delay, power, and energy. It has been reported that interconnects in any VLSI system account for more than 60% of signal delay [3, 4]. The paper has been prepared in the following way.

Section 2 explains the types of interconnects. Section 3 describes the interconnect models and parameters. Simulation results have been presented and discussed in Sect. 4. The conclusions have been presented in Sect. 5. This brief is organized as follows. Section 2 describes the VCO types. Section 3 describes the proposed ring VCO design. The simulation results are given in Sect. 4 and the conclusion is given in Sect. 5.

2 Interconnect Types

Interconnect or wiring is used in any system or circuit to propagate the clock and other signals which give data, power, or ground to all the circuits in a system. This interconnect is classified based on its length, namely (i) local, (ii) semi global, and (iii) global [5, 6]. Local interconnect offers less parasitic due to the smaller size, does not travel very long distances, and cover smaller distance only in a chip. Semi global interconnect gives parasitic because of wider and taller than local interconnects. This interconnect provides the interconnection between substantial modules and I/O circuitry. Global interconnects have more parasitic because of larger size than others [7, 8]. These are used to provide clock, power, and long distance communication between functional blocks. These occupy the top layers in a chip. These interconnect parasitic introduce noise sources, increase the propagation delay and power dissipation, and thereby increase the power delay product, which have more effect on circuit performance and reliability. There are different simulation interconnect models which have been considered over the past several decades to calculate these parasitic accurately. Single interconnect is used for circuit-level estimation and parallel interconnect structures are used for bus structures [9,10,11]. In this paper both structures are have been considered for simulation and analysis using spice tool.

3 Interconnect Model

To study the behavior of on-chip interconnect as function of its parameters, electrical models are required. An interconnect can be modeled as R, RC, LC, RLC, or RLGC networks. Generally, signal and clock interconnects are used to model as RC or RLC. These can be represented either in lumped or distributed model [12].

The interconnect parasitic are generally disbursed along its length. They are not lumped into a solitary position. But for fast observation of the effects of RLC parameters, it is frequently helpful to lump the distinctive parts into a solitary circuit element. In view of low switching frequency, only resistance and capacitance will be considered and neglecting inductance. For low frequencies, it is possible to lump parasitic parameters into a single RC model by neglecting the L. There are different configurations of RC Interconnect models namely L, T, and pi [2, 6]. Any model may be considered to calculate propagation delay. But in lower technologies, lumped models are not considered because of inaccuracy. For a RC interconnect a distributed RC model is more accurate. Because the simulation results of a distributed model match more accurate than the lumped model, for computer-aided analysis distributed RC interconnect can be approximated by a lumped multistage RC ladder network. An Elmore delay model has been considered in this paper for analysis purpose which is shown in Fig. 1. This model has linear relation between length and delay [12].

Fig. 1
figure 1

Multistage RC ladder network

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Delay of a RC network is given by

$$ D = R_{1} C_{1} + (R_{1} + R_{2} )C_{2} + (R_{1} + R_{2} + R_{3} )C_{3} + \cdots + (R_{1} + R_{2} + \cdots + R_{n} )C_{n} . $$
(1)

3.1 Interconnect Characteristics

All the wires’ resistance, capacitance, and inductance values are extracted from interconnect geometry structures. Resistance relates to current I to voltage V (carrier flow) [13]. For any current-carrying conductor having some resistance, the resistance is given by Eq. 2:

$$ R = \frac{\rho l}{wt}, $$
(2)

where ρ represents the resistivity, l is the length, W is the width, and H is the thickness of the interconnect [14]. Generally, capacitance relates charge Q to voltage V (electric energy). Interconnect capacitance consists of two components namely (i) ground capacitance Cg (capacitance between metallic layers and substrate) and (ii) coupling capacitance Cc (capacitance between neighboring interconnects). The coupling capacitance is dominating Cg in the lower technologies because of increasing aspect ratio and decreasing wire spacing. The analytical expressions given in Eqs. 3 and 4 are used to calculate the ground capacitance Cg and coupling capacitance Cc for copper interconnects, which are given below [15]:

$$ C_{g} = \varepsilon \left[ {\frac{w}{h} + 2.22\left( {\frac{s}{s + 0.7h}} \right)^{3.19} + 1.17\left( {\frac{s}{s + 1.51h}} \right)^{0.76} \left( {\frac{t}{t + 4.53h}} \right)^{0.12} } \right] $$
(3)
$$ C_{c} = \varepsilon \left[ {1.14\frac{t}{s}\left( {\frac{h}{h + 2.06s}} \right)^{0.09} + 0.74\left( {\frac{w}{w + 1.59s}} \right) - 1.16\left( {\frac{w}{w + 1.87s}} \right)^{0.16} \left( {\frac{h}{h + 0.98s}} \right)^{1.18} } \right]. $$
(4)

Similarly, inductance relates current I to flux H (magnetic energy), and when compared to other parameters, inductance is difficult to extract from the interconnect structures. In case of high-frequency transmission, global interconnects will higher inductance than local interconnects. In this paper, only RC interconnect model has been considered and analyzed for the delay variations in DSM technology.

4 Simulation Results and Discussion

In this paper an attempt has been made to simulate CMOS inverter as driver, consisting interconnect with equivalent R and C derived from analytical expressions and load CL and the circuit is shown in Fig. 2.

Fig. 2
figure 2

RC interconnects with CMOS driver and load

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The simulation has been carried out in three different ways, namely (i) single interconnect with CMOS driver and load as shown in Fig. 2; (ii) two parallel interconnects with coupling capacitance operating in same switching; and (iii) two parallel interconnects with opposite switching. The technologies considered in this simulation as case 1 are 180, 130, and 65 nm. The lengths of copper wires considered for these technologies are 2, 5, and 10 mm.

In case 2, the technologies considered are as 45, 32, and 22 nm with copper wire lengths of 1, 50, and 100 µm. At lower technologies the lengths of interconnects will be smaller. The simulation results are presented in Tables 1 and 2 and in Figs. 3, 4, 5, and 6. Around 10% variations in delay and PDP values have been observed irrespective of technologies employed with different interconnect lengths, whereas around 5% variation has been observed in delay and PDP values for different interconnect patterns (single, parallel with different switchings) in the same technology with different interconnect lengths. With technology scale down (45, 32, and 22 nm), it is observed that variations in the delay and PDP values are more than 50%. All the simulations were carried out using BSIM4 model files in LT spice simulation tool for above-mentioned technologies.

Table 1 Delay and energy for different technology nodes (180, 130, 65 nm) with variation of interconnect length
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Table 2 Delay and energy for different technology nodes (45, 32, 22 nm) with variation of interconnect length
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Fig. 3
figure 3

Variation in delay by change in interconnect length for single interconnect

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Fig. 4
figure 4

Variation in delay by change in interconnect length for coupled interconnect when opposite switching

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Fig. 5
figure 5

Variation in PDP by change in interconnect length for coupled interconnect when opposite switching

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Fig. 6
figure 6

Variation in delay by change in interconnect length for coupled interconnect when same switching

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5 Conclusions

In this paper, an attempt has been made to simulate different copper interconnect structures (single and parallel with different switching events), with a CMOS inverter as driver and load CL and analyzed the effect of interconnect parasitic on circuit performance metrics such as delay and power delay product. It is observed around 10% variation with different interconnect lengths, 5% variation with different interconnect structures when technology is remains constant in the values of delay and PDP. On the other hand, with variations in technology, around 50% variation has been observed in the values of delay and PDP.