High-Throughput Low-Power Variable Rate Network Intrusion Detection System Using Unique SRAM Controller

Abstract

Network intrusion detection system (NIDS) is a major research area for security mechanism. In recent years, the demand for digital systems in network field increase due to the development of 4G technology and high network traffic rate. In this paper, we propose a bit-based pattern matching algorithm with unique SRAM architecture for parallel processing. To reduce the bit transitions during matching process state encoded finite-state machines (FSMs) were used which the main core in the pattern is matching process, where a number of states remain constant over pattern length. To avoid synchronization problem over variable rate pattern match unique controllers are used which is driven by adaptive digital phase locked loop (ADPLL). The functionality is proved through the test bench simulation using Modelsim and power efficiency is verified using FPGA synthesis. In this work, memory size requirements are reduced by 8 times with an early detection scheme and the overall throughput rate is attained in the range of 13 Gbps. Finally, the dynamic power consumption is greatly reduced by 7% through gated logic.