Level Skip VLSI Architecture for 2D-Discrete Wavelet Transform

  • G. Kiran MayeEmail author
  • T. Srinivasulu
Conference paper
Part of the Lecture Notes in Networks and Systems book series (LNNS, volume 8)


A low power and efficient 2-D Discrete Wavelet Transform architecture is proposed. Previous DWT architectures utilized flipping structures or modified lifting based schemes. In this over-lapped strip based scanning is utilized to reduce the number of clock cycles for reading the input pixels. In addition that, second level prediction and updating equations are derived directly. It is observed that the number of adders and multipliers are reduced. The hardware utilization and power consumption is decreased in order to improve the performance of the discrete wavelet transform. The execution results expose that the suggested architecture is enhanced in area competence of 1% slices, 1% of DSP 48 s, multipliers and adders are also decreased.


Discrete wavelet transform Word length Xilinx FPGA Area Power consumption 


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© Springer Nature Singapore Pte Ltd. 2017

Authors and Affiliations

  1. 1.Department of ECEGuru Nanak Institutions Technical CampusIbrahimpatnamIndia
  2. 2.Kakatiya College of Engineering, KUWarangalIndia

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