Abstract
Varieties of charge pump architectures are discussed and simulated with constant loop parameters. DC mismatch is significantly compared for single-ended and fully differential charge pumps. The charge pumps are designed with foundry tsmc, 90 nm and 1.8 V CMOS technology. The improved versions of single-ended and differential charge pumps are explicating providing high performance. The current mismatch is achieved less than 0.01–0.2% for different architectures.
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Rajeshwari, D.S., Rao, P.V. (2018). Architectures of Charge Pump for Digital Phase Locked Loops. In: Saini, H., Singh, R., Reddy, K. (eds) Innovations in Electronics and Communication Engineering . Lecture Notes in Networks and Systems, vol 7. Springer, Singapore. https://doi.org/10.1007/978-981-10-3812-9_3
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DOI: https://doi.org/10.1007/978-981-10-3812-9_3
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