Body Biased High Speed Full Adder to LNCS/LNAI/LNBI Proceedings
In various domains like VLSI design, Embedded Systems, Signal processing, Image processing etc. combinational and logical circuit are the basic building blocks whereas addition is the fundamental step involved in any of it. Increasing the efficiency of these fundamental blocks is one of the major concerns in the application development. Moreover, power and delay are the major concern in the VLSI design so as to increase the efficiency of the circuit. In the combinational system performance and speed of the circuit is directly related with delay. In this paper hybrid adder circuit is designed using both Complementary Metal Oxide Semiconductor (CMOS) logic and transmission gates which performs addition at a low power and reduced delay. Further the speed of operation of the circuit is improved by introducing Gate Level Body Biasing (GLBB) in the design. The design was first implemented for full adder and then extended for 8 bit ripple carry adder. The circuit was implemented using Cadence Virtuoso tools in 180 nm technology. For 1.8 V supply at 180 nm technology, the average delay of the circuit is (114.5 ps), having moderate power consumption (27.52 mW) is found to have extremely low values than that resulted from the use of very weak CMOS inverters coupled with strong transmission gates. With additional GLBB circuit incorporated with the design proved useful in boosting the circuit. In comparison with the existing full adder the proposed Full adder found to offer significant improvement in terms of speed at the cost of power.
KeywordsDelay Hybrid full adder High speed adder Transmission gates Body biasing
The author would like to thank the management, Director, Principal, Head of Department of Institute of aeronautical college, Hyderabad for their support and guidance in completion of this research paper.
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