Advertisement

Performance of Optimized Reversible Vedic Multipliers

  • A. Sai Ramya
  • B. S. S. V. Ramesh Babu
  • E. Srikala
  • M. Pavan
  • P. Unita
  • A. V. S. Swathi
Conference paper
Part of the Lecture Notes in Networks and Systems book series (LNNS, volume 5)

Abstract

Signal processing applications involve in many arithmetic operations. High speed arithmetic operations play an important role in these applications. Multipliers are often considered as the basic building blocks of digital signal processors (DSP). The speed of the multiplier corresponds to DSP. Multiplication is the basic operation to be performed in DSP. In order to implement these multiplications many algorithms are used. In this paper, few algorithms are discussed to implement multiplication. The algorithm discussed in this paper is the most ancient methodology used by Aryans. In this paper reversible Vedic multiplier is proposed using Urdhva Tiryakbhyam (UT) sutra and a comparative study reveals and suggests different logics pertaining to different profile considerations such as power and area.

Keywords

Vedic mathematics Algorithms Urdhva Tiryakbhyam Low power Area 

References

  1. 1.
    Ramalatha, M., DeenaDayalan, K., Daharani, P.: High Speed Energy Efficient ALU Design using Vedic Multiplication Techniques. In: ACTEA IEEE, pp. 600–603.Google Scholar
  2. 2.
    Wallace, C.S.: A Suggestion for a Fast Multiplier. In: IEEE Trans. Elec. Comput., Vol EC 13, pp. 14–17 (1964).Google Scholar
  3. 3.
    Panwit Tuwanuti., Nopphagaw Thongbai.: Implementation of Vedic Multiplier Technique on Multicore Processor. In: TENCON IEEE Region 10 conference, Oct (2014).Google Scholar
  4. 4.
    Honey Durga Tiwari., Ganzorig Gankhuyag., Chan Mo Kim.., Yong beom Cho.: Multiplier Design Based on Ancient Indian Vedic Mathematics. In: SoC Design Conference 2008, ISOCC’08 International, vol- 2 (2008).Google Scholar
  5. 5.
    Rudagi, J.M., Viswanath Ambi., Viswanath Munavalli., Ravindra patil., Vinaykumar Sajjan.: Design and Implementation of Efficient Multiplier Using Vedic Mathematics. In: Advances in Recent Technologies in Communication and Computing 3rd International Conference IEEE (2012).Google Scholar
  6. 6.
    Yogita Bansal., Charu Madhu., pradeep kaur.: High Speed Vedic Multiplier Designs-A review. In: Engneering and Computational Sciences (2014).Google Scholar
  7. 7.
    Tritha, B.K.: Vedic Mathematics. (1965).Google Scholar
  8. 8.
    Mehta, P., Gawali, D.: Conventional versus Vedic Mathematical Method for Hardware Implementation of a Multiplier. In: IEEE International Conference on Advances in Computing, Control, and Telecommunication Technologies, pp. 640–642(2009).Google Scholar
  9. 9.
    Sao, S.S.R.M., Siddamal, S.: High Speed Signal Multiplier for Digital Signal Processing Applications. In: IEEE International conference on signal.Google Scholar
  10. 10.
    In: IEEE International conference on Devices circuits and Systems, pp. 360–364 (2012) processing comput, pp.1-6 (2012).Google Scholar

Copyright information

© Springer Nature Singapore Pte Ltd. 2017

Authors and Affiliations

  • A. Sai Ramya
    • 1
  • B. S. S. V. Ramesh Babu
    • 1
  • E. Srikala
    • 1
  • M. Pavan
    • 1
  • P. Unita
    • 1
  • A. V. S. Swathi
    • 1
  1. 1.Department of ECERaghu Institute of TechnologyVisakhapatnamIndia

Personalised recommendations