Design of Scan Cell for System on Chip Scan Based Debugging Applications

  • A. Murali
  • K. Hari Kishore
  • G. Vijaya Padma
  • L. Srikanth
  • R. H. Gopalkrishna
Conference paper
Part of the Lecture Notes in Networks and Systems book series (LNNS, volume 5)

Abstract

This paper presents a scan based debugging technique approach for a SOC with multiple clock domains. In this paper, the existing techniques are used for debugging the SOC has been described and the limitations of existing debugging approach have also explained. To overcome the limitations of the existing debugging techniques, new scan cell approach has been proposed. This debugging technique also supports online debugging and it holds the present status and shifts previous state. The IEEE 1500 test wrapper has been optimized to minimum area with the proposed debugging technique.

Keywords

System-on-chip (SOC) debugging Design-For-Debug (DFD) Scan-based debugging Scan design Online debugging 

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Copyright information

© Springer Nature Singapore Pte Ltd. 2017

Authors and Affiliations

  • A. Murali
    • 1
    • 2
  • K. Hari Kishore
    • 1
  • G. Vijaya Padma
    • 1
  • L. Srikanth
    • 2
  • R. H. Gopalkrishna
    • 2
  1. 1.Department of ECEKLEF, K.L UniversityGunturIndia
  2. 2.Department of ECERAGHU Engineering CollegeVisakhapatnamIndia

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