Design of Cascaded Hybrid Interleaver for Fast Turbo Coding and Decoding

  • M. Rajani Devi
  • K. Ramanjaneyulu
  • B. T. Krishna
Conference paper
Part of the Lecture Notes in Networks and Systems book series (LNNS, volume 5)


Turbo code in an attempt to realize a technique that approaches the theoretic limit utilizes a crucial component, interleaver, which converts burst errors caused by impulsive noise to simple errors. But the processing of data through the interleaver incurs time as well as memory. Both time and memory complexities are directly related to the total number of information bits. The time required for interleaver processing is so high because of which some applications omits the complete interleavers. But the consequent schemes suffer from high bit error rate. In this chapter a novel hybrid two stage interleaving scheme was proposed which reduces the time required for interleaving processing while maintaining the BER criteria up to the levels obtained with block or 3GPP interleavers.


Interleaver Turbo code Block interleaver 3GPP interleaver 


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Copyright information

© Springer Nature Singapore Pte Ltd. 2017

Authors and Affiliations

  • M. Rajani Devi
    • 1
  • K. Ramanjaneyulu
    • 2
  • B. T. Krishna
    • 3
  1. 1.JNTU KakinadaKakinadaIndia
  2. 2.PVP Siddhartha Institute of TechnologyVijayawadaIndia
  3. 3.JNTUVizianagaramIndia

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