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Improved In-System Debugging of High Level Synthesis Generated FPGA Circuits

  • A. Murali
  • K. Hari Kishore
  • A. Trinadha
  • Saswat Tripathy
  • P. Dhanunjaya Rao
Conference paper
Part of the Lecture Notes in Networks and Systems book series (LNNS, volume 5)

Abstract

The new approaches for in-system debug of High-Level Synthesis generated hardware have been proposed. With these approaches the source level events are observed in the final hardware by using Event Observability Ports (EOP). And also Event Observaility Buffers (EOB) is proposed for tracing events with the use of EOPs. In EOBs the data storage is done in cycle-by-cycle manner on the basis of EOB-by-EOB. This approach leads to the loss of different event timing relationships information stored in various trace buffers. These event relationships are recovered by the proposed two methods in this chapter. The observed results in this chapter will describe the effectiveness and feasibilities of EOB trace strategy.

Keywords

Event observability ports (EOP) Event observability of buffers (EOB) Trace buffer Field programmable gate array Design verifications 

References

  1. 1.
    J. Cong, L. Bin, S. Neuendorffer, J. Noguera, K. Vissers, and Z. Zhiru.: High-level synthesis for fpgas from prototyping to deployment. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions. vol. 30, no. 4, 473–491 (2011)Google Scholar
  2. 2.
    K. Rupnow, L. Yun, L. Yinan, and C. Deming.: A study of high-level synthesis Promises and challenges, in ASIC (ASICON), 2011 IEEE 9th International Conference on, Conference Proceedings, pp. 1102–1105 (2011)Google Scholar
  3. 3.
    J. Cong and Z. Zhang.: An efficient and versatile scheduling algorithm based on sdc formulation. pp. 433–438 (2006)Google Scholar
  4. 4.
    K. S. Hemmert, J. L. Tripp, B. L. Hutchings, and P. A. Jackson.: Source level debugger for the sea cucumber synthesizing compiler in Field- Programmable Custom Computing Machines, 2003. FCCM 2003. 11th Annual IEEE Symposium on, Conference Proceedings, pp. 228–237 (2003)Google Scholar
  5. 5.
    K. S. Hemmert, “Source level debugging of circuits synthesized from high level language descriptions. (2004)Google Scholar
  6. 6.
    E. Hung and S. J. Wilton, “Incremental trace-buffer insertion for fpga debug.(2003)Google Scholar
  7. 7.
    J. Keeley.: An incremental trace-based debug system for field programmable gate-arrays. (2013)Google Scholar
  8. 8.
    J. Curreri, G. Stitt, and A. D. George.: High-level synthesis techniques for in-circuit assertion-based verification in Parallel & Distributed Processing, Workshops and PhD Forum (IPDPSW), 2010 IEEE International Symposium on, Conference Proceedings, pp. 1–8 (2010)Google Scholar
  9. 9.
    Xilinx.: Vivado design suite user guide: High-level synthesis. vol. UG902–Version 2013.4 (2013)Google Scholar

Copyright information

© Springer Nature Singapore Pte Ltd. 2017

Authors and Affiliations

  • A. Murali
    • 1
    • 2
  • K. Hari Kishore
    • 1
  • A. Trinadha
    • 3
  • Saswat Tripathy
    • 2
  • P. Dhanunjaya Rao
    • 2
  1. 1.Department of ECE, KLEFK.L UniversityGunturIndia
  2. 2.Department of ECERaghu Engineering CollegeVisakhapatnamIndia
  3. 3.Department of ECEChinthalapudi Engineering CollegeGunturIndia

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