Abstract
This paper presents a novel analysis of a self-compensating, low-noise, low-power Phase-Locked-Loop circuit design implemented @ 45-nm technology node. The basic Phase-Locked-Loop (PLL) circuit prescribed in the literature comprises a Phase Detector or comparator followed by a low-pass filter and a voltage-controlled oscillator. The individual circuit elements have been separately designed in Virtuoso Analog Design Environment of Cadence Design System and analyzed for achieving optimum performance and then combined in cascade to form a feedback network. Simulation results obtained for the individual components have been critically investigated in the later half of the paper, which shows considerable improvement in frequency stability and power consumption of the PLL design. Finally, conclusions have been drawn based upon the integrated design and stress has been laid upon future scopes of work in this area.
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References
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Acknowledgements
We are thankful to DST, New Delhi, and DRDL, Hyderabad, for funding the IC design tools like Cadence Virtuoso to Dr. Vijay Nath. We are also thankful to Dr. M.K Mishra, Vice Chancellor, BIT Mesra and Prof. V.R Gupta, H.O.D ECE, BIT Mesra, for providing continuous inspiration and encouragement.
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Mal, A., Chitransh, A., Srivastava, H., Saw, S.K., Nath, V. (2017). Analysis of a Self-compensating, Low-Noise, Low-Power PLL Circuit @ 45-nm Technology Node. In: Nath, V. (eds) Proceedings of the International Conference on Nano-electronics, Circuits & Communication Systems. Lecture Notes in Electrical Engineering, vol 403. Springer, Singapore. https://doi.org/10.1007/978-981-10-2999-8_30
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DOI: https://doi.org/10.1007/978-981-10-2999-8_30
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