Abstract
This work deals with the analysis, design and implementation of Thyristor Binary Switched Capacitor (TBSC) banks. The performance of various TBSC topologies for reactive power compensation suitable for fast dynamic loads in closed loop systems are investigated by simulation. The scheme consists of Thyristor Binary Switched Capacitor (TBSC) banks. TBSC is based on a chain of Thyristor Switched Capacitor (TSC) banks arranged in binary sequential manner. Frequent switching of capacitors results the life of switched capacitor bank. Hence, a control circuitry has been proposed in such a way that transient free switching of TBSCs will takes place. Proposed topology allows almost step-less reactive power compensation for fast varying dynamic loads in closed loop. This scheme has error in reactive power compensation equals to half of the lowest step size of the capacitor bank. The suitable chain of binary switched capacitor bank will be proposed. The proposed scheme can achieve reactive power compensation cycle to cycle basis and the harmonics contents of source are maintained at insignificant levels due to filtering action of TBSC as well as transient free switching of capacitor bank. Proposed TBSC scheme compensates the fast varying dynamic reactive load. Also the proposed scheme can be used for direct online starting of I.M.s with voltage sag mitigation at starting, which helps improving stability of the system and Power Factor (P.F.) improvement in steady state.
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Acknowledgements
This work was supported by Department of Electrical Engineering, Annasaheb Dange College of Engineering and Technology, Ashta, Maharashtra, India.
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Patil, S., Shende, K., Patil, D., Mulla, A. (2017). TBSC Compensator. In: Ao, SI., Kim, H., Amouzegar, M. (eds) Transactions on Engineering Technologies. WCECS 2015. Springer, Singapore. https://doi.org/10.1007/978-981-10-2717-8_22
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DOI: https://doi.org/10.1007/978-981-10-2717-8_22
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