Abstract
This paper presents an in-depth analysis of NMOS capacitances across various technology nodes and device parameters which are extracted for different operating regions namely accumulation, cutoff, saturation and triode, while keeping the aspect ratio same for each transistor. Since MOS capacitances are the key parameters for estimating process development, material selection and device modeling, this paper enlists their variation with gate-to-source voltage (VGS) while keeping drain-to-source voltage (VDS) constant. This paper also aims to present the impact of capacitance variation on device performance that includes operating speed, power consumption, delay product and so on. The simulations results have been extensively verified using HSPICE simulator @ various technology nodes.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
R. Chau, Datta S., M. Doczy, Doyle B., Kavalieros J., M. Metz, “High-κ/metal-gate stack and its MOSFET characteristics,” IEEE Electron Dev. Lett., vol. 25, no. 6, pp. 408–410, 2004.
Y. Taur, Ning T. H., “Funds. of modern VLSI devices,” Cambridge university press, 2009.
I. Saad, Riyadi M. A., F. M. N. Zul A., R. Ismail, “Reduced parasitic capacitances analysis of nanoscale vertical MOSFET,” Semiconductor Electronics (ICSE) IEEE Int. Conference on, pp. 25–29, Jun. 2010.
Y. Ohkura, Toyabe T., H. I. R. O. O. Masuda, “Analysis of MOS capacitances and their behavior at short-channel lengths using ac device simulator,” IEEE Trans. Comput.-Aided Design Integr. Ckts Syst., vol. 6, no. 3, pp. 423–430, 1987.
Rabaey J. M., Chandrakasan A. P., Borivoje N., “Digital integr. ckts,” vol. 2, Englewood Cliffs: Prentice hall, 2002.
D. E. Ward, “Charge-based mod. of cap. in MOS T,” Integr. ckts. labs, June 1981.
J. He, X. Xi, M. Chan, K. Cao, Niknejad A., Hu C., “A physics based analytical surface pot. and cap. model of MOS operation from acc. to dep. region,” Proc. Nanotech NSTI, vol. 2, pp. 302–305, Feb. 2003.
F. Gilibert, D. Rideau, F. Payet, F. Boeuf, E. Batail, M. Minondo, Jaouen H., “Strained Si/SiGe MOS cap. modeling based on band structure analysis,” Solid-State Dev. European Research 35th Conf. (ESSDERC 2005) Proc., pp. 281–284, Sep. 2005.
L. Larcher, P. Pavan, Pellizzer F., Ghidini G., “A new mod. of gate cap. as a simple tool to extract MOS param.,” IEEE Trans. Electr. Dev., vol. 48, no. 5, pp. 935–945, 2001.
A. K. Dwivedi, P. Abhijeet, R. Mehra, A. Islam, “Versatile Noise Suppressed Variable Pulse Voltage Controlled Oscillator,” Int. Journal of App. Engg. Research (IJAER), vol. 10, no. 20, pp. 18633–18638, May. 2015.
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2017 Springer Science+Business Media Singapore
About this paper
Cite this paper
Sarita Kumari, Rishab Mehra, Dwivedi, A.K., Aminul Islam (2017). Estimation of MOS Capacitance Across Different Technology Nodes. In: Mandal, J., Satapathy, S., Sanyal, M., Bhateja, V. (eds) Proceedings of the First International Conference on Intelligent Computing and Communication. Advances in Intelligent Systems and Computing, vol 458. Springer, Singapore. https://doi.org/10.1007/978-981-10-2035-3_30
Download citation
DOI: https://doi.org/10.1007/978-981-10-2035-3_30
Published:
Publisher Name: Springer, Singapore
Print ISBN: 978-981-10-2034-6
Online ISBN: 978-981-10-2035-3
eBook Packages: EngineeringEngineering (R0)