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Comparative Study of the Methodologies Used in Low-Power Master–Slave Flip-Flops

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Part of the Advances in Intelligent Systems and Computing book series (AISC,volume 479)

Abstract

Low-power flip-flop plays a crucial role in low-power digital system. Flip-flops are the basic unit in the design of digital circuits which consumes a large amount of power in redundant transitions and clocking. In order to achieve power-efficient designs, reducing its power to improve the performance is an important issue in very large scale integration field. In this paper, the comparative study of few existing design techniques of master–slave falling edge triggering of D flip-flops are done. The synchronous nature of clock signal used to activate along with the input data signal in the techniques is used. Among different techniques, push-pull isolation flip-flop provides least transition delay and high performance which improves the overall efficiency. Simulations were performed in cadence virtuoso gpdk 180 nm/1.8 V CMOS technology.

Keywords

  • Flip-Flop
  • Low power
  • Delay
  • Transistor
  • Circuit

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  • DOI: 10.1007/978-981-10-1708-7_13
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References

  1. Kang, S.M., Leblebici, Y.: CMOS Digital Integrated Circuits: Analysis and Design. Reading, Tata McGraw –Hill Edition. 2nd edn (2003)

    Google Scholar 

  2. Singh, K., Tiwari, S.C., Gupta, M.: A Modified Implementation of Tristate Inverter Based Static Master-Slave Flip-Flop with Improved Power-Delay-Area Product. A Research Article published on The Scientific World Journal (2014) 1–14

    Google Scholar 

  3. Khan, I.A., Shah, O.A., Beg, M.T.: Analysis of Different Techniques for Low Power Single Edge Triggered Flip Flops. IEEE Conference published on World Congress of Information and Communication Technologies (2011) 1363–1367

    Google Scholar 

  4. Consoli, E., Palumbo, G., Pennisi, M.: Reconsidering high speed design criteria for transmission-gate-based master-slave flip-flops. Vol.20. IEEE Transactions on Very Large Scale Integration (VLSI) Systems (2012) 284–295

    Google Scholar 

  5. Stojanovic, V., Oklobdzija, V.G.: Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems. Vol.34. IEEE Journal of Solid-State Circuits (1999) 536–548

    Google Scholar 

  6. Weste, N., Eshraghian, V.: Principles of CMOS VLSI Design: A Systems Perspective. Reading, MA: Addison-Wesley. 4th edn (1993).

    Google Scholar 

  7. Singh, K., Tiwari, S.C., Gupta, M.: A High Performance Flip Flop for Low Power Low Voltage Systems. World Congress on Information and Communication Technologies (WICT), IEEE conference (2011) 257–262

    Google Scholar 

  8. Ko, U., Balsara, P.T.: High-Performance Energy-Efficient D-Flip-Flop Circuits. Vol.8. IEEE Transaction on Very Large Scale Integration (VLSI) Systems. IEEE Transaction on Very Large Scale Integration (VLSI) Systems (2000) 94–98

    Google Scholar 

  9. Gerosa, G., Gary, S., Dietz, C., Pham, D., Hoover, K., et al.: 2.2 W, 80 MHz superscalar RISC processor. Vol.29. IEEE Journal of Solid-State Circuits (1994) 1440–1454

    Google Scholar 

  10. Khan, I.A., Beg, M.T.: Design and Analysis of Low Power Master Slave Flip-Flops. Vol.43. Informacije Midem-Journal of Microelectronics Electronic Components and Materials (2013) 41–49

    Google Scholar 

  11. Khan, I.A., Beg, M.T.: Comparative Analysis of Low Power Master Slave Single Edge Triggered Flip Flops. Vol.16. World Applied Analysis of Different Techniques for Low Power Single Edge Triggered Flip Flops Science Journal (2012) 15–21

    Google Scholar 

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Correspondence to Arpita Sengupta .

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Arpita Sengupta, Peyush Pande (2017). Comparative Study of the Methodologies Used in Low-Power Master–Slave Flip-Flops. In: Singh, R., Choudhury, S. (eds) Proceeding of International Conference on Intelligent Communication, Control and Devices . Advances in Intelligent Systems and Computing, vol 479. Springer, Singapore. https://doi.org/10.1007/978-981-10-1708-7_13

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  • DOI: https://doi.org/10.1007/978-981-10-1708-7_13

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