Abstract
In the previous chapter, we have introduced to the readers several examples of countermeasures against differential fault analysis. These countermeasures are all redundancy-based, and use a concurrent error detection mechanism to infer the presence of a fault. It is important to note here that these classical redundancy-based countermeasures are designed under the assumption that all faults in a given fault space occur with equal probability. In real-life implementations, such instances of fault attacks are usually rare to find, wherein an adversary an inject faults uniformly at random. Rather, practical fault injection attacks are often found to exhibit a characteristic bias in the fault-distribution, which may be related to the device/design specifications. In this chapter, we demonstrate to the readers how fault bias acts as a threat to the security of classical countermeasures.
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Patranabis, S., Chakraborty, A., Mukhopadhyay, D., Chakrabarti, P.P. (2018). Fault Space Transformation: Countering Biased Fault Attacks. In: PATRANABIS, S., Mukhopadhyay, D. (eds) Fault Tolerant Architectures for Cryptography and Hardware Security. Computer Architecture and Design Methodologies. Springer, Singapore. https://doi.org/10.1007/978-981-10-1387-4_9
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DOI: https://doi.org/10.1007/978-981-10-1387-4_9
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