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Multi-core Scheduling Scheme for Wireless Sensor Nodes with NVRAM-Based Hybrid Memory

Conference paper
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Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 331)

Abstract

In recent years, multi-core processor technology and next generation non-volatile memory technology have developed dramatically to boost performance while minimizing power consumption. In this paper, we study a hybrid memory-aware multi-core scheduling scheme for wireless sensor nodes which use DRAM/NVRAM hybrid main memory. The proposed HAMC (Hybrid memory-Aware Multi-Core) scheduling scheme considers different access latency of hybrid memory medium and tries to reduce total execution time of tasks. We showed through simulation that proposed scheme outperforms legacy scheduling scheme.

Keywords

Multi-core scheduling Wireless sensor node NVRAM Hybrid main memory 

Notes

Acknowledgments

This research was supported by Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education, Science and Technology (2010-0021897).

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Copyright information

© Springer Science+Business Media Dordrecht 2015

Authors and Affiliations

  1. 1.Department of Computer EngineeringMyongji UniversityYoinginKorea

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