Abstract
In recent years, multi-core processor technology and next generation non-volatile memory technology have developed dramatically to boost performance while minimizing power consumption. In this paper, we study a hybrid memory-aware multi-core scheduling scheme for wireless sensor nodes which use DRAM/NVRAM hybrid main memory. The proposed HAMC (Hybrid memory-Aware Multi-Core) scheduling scheme considers different access latency of hybrid memory medium and tries to reduce total execution time of tasks. We showed through simulation that proposed scheme outperforms legacy scheduling scheme.
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Acknowledgments
This research was supported by Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education, Science and Technology (2010-0021897).
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Oh, S., Ryu, Y. (2015). Multi-core Scheduling Scheme for Wireless Sensor Nodes with NVRAM-Based Hybrid Memory. In: Park, J., Pan, Y., Chao, HC., Yi, G. (eds) Ubiquitous Computing Application and Wireless Sensor. Lecture Notes in Electrical Engineering, vol 331. Springer, Dordrecht. https://doi.org/10.1007/978-94-017-9618-7_5
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DOI: https://doi.org/10.1007/978-94-017-9618-7_5
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