EOS Protection for USB2 Transceiver
This paper presents CMOS integrated electrical over stress (EOS) protection circuit for USB2 transceiver. A unique full speed SE0 state in USB2 standard protocol produces overshoot and undershoots in presence of an on board choke. The purpose of choke is to minimize EMI for USB2 differential signaling. This works fine as long as data signaling is differential. In the presence of SE0 state, single transition occurs on either Dp or Dn pad causing high inductive kick back from choke resulting in excessive overshoot and undershoots. The electrical over stress on cascode devices leads to device degradation resulting in violation of USB2 output driver impedance spec of 45 Ω ±5 %. This in turn increases ‘defects per million’ count over time. To mitigate this reliability issue, EOS protection circuit is proposed. This circuit is designed in Intel-22 nm process and evaluated by computer simulations across all PVT conditions. Proposed EOS protection circuit reduces respective overshoot and undershoot of 4.2 V and −0.6 to 3.7 V and −0.34 V. For the growing EOS concern of deep submicron devices in 14, 10 nm and future technologies, this design scheme becomes an attractive choice.
KeywordsCMOS integrated circuits EOS EOP Mealy state m/c SE0 state USB2
The author wishes to thank Intel Microelectronics, HIP USB2 circuit team, Malaysia for providing necessary access to tools and Intel 22 nm process technology. Author also would like to thank IMC WPRD ETS DSI IPR PHY group, Germany for their encouragement and support on this work.
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